PIC32MM0064GPM028 CLC2 registers

The 3 registers of CLC2 (Configurable logic cell 2), from 0xBF802500, with their reset value and every field. The PIC32MM0064GPM028 has 419 registers in 52 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

CLC2 Configurable logic cell 2

CLC2CON

Address
0xBF802500
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
G4POL19Gate 4 Polarity Control bit
  • 0 The output of Channel 4 logic is not inverted
  • 1 The output of Channel 4 logic is inverted when applied to the logic cell
G3POL18Gate 3 Polarity Control bit
  • 0 The output of Channel 3 logic is not inverted
  • 1 The output of Channel 3 logic is inverted when applied to the logic cell
G2POL17Gate 2 Polarity Control bit
  • 0 The output of Channel 2 logic is not inverted
  • 1 The output of Channel 2 logic is inverted when applied to the logic cell
G1POL16Gate 1 Polarity Control bit
  • 0 The output of Channel 1 logic is not inverted
  • 1 The output of Channel 1 logic is inverted when applied to the logic cell
ON15CLCx Enable bit
  • 0 CLCx is disabled and has logic zero outputs
  • 1 CLCx is enabled and mixing input signals
INTP11CLCx Positive Edge Interrupt Enable bit
  • 0 Interrupt will not be generated
  • 1 Interrupt will be generated when a rising edge occurs on LCOUT
INTN10CLCx Negative Edge Interrupt Enable bit
  • 0 Interrupt will not be generated
  • 1 Interrupt will be generated when a falling edge occurs on LCOUT
LCOE7CLCx Port Enable bit
  • 0 CLCx port pin output is disabled
  • 1 CLCx port pin output is enabled
LCOUT6CLCx Data Output Status bit
  • 0 CLCx output low
  • 1 CLCx output high
LCPOL5CLCx Output Polarity Control bit
  • 0 The output of the module is not inverted
  • 1 The output of the module is inverted
MODE2:0CLCx Mode bits
  • 0 Cell is a AND-OR
  • 1 Cell is an OR-XOR
  • 2 Cell is a 4-input AND
  • 3 Cell is an SR latch
  • 4 Cell is a 1-input D flip-flop with S and R
  • 5 Cell is a 2-input D flip-flop with R
  • 6 Cell is a JK flip-flop with R
  • 7 Cell is a 1-input transparent latch with S and R

CLC2SEL

Address
0xBF802510
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
DS414:12Data Selection MUX 4 Signal Selection bits
  • 0 CLCINB I/O pin
  • 1 CLC1 out
  • 2 SCCP5 OCM5 Output
  • 3 SPI2 SDI2 in
  • 4 CMP3 out
  • 5 RTCC event
  • 6 MCCP1 OCMP compare match event
  • 7 SCCP5 OCMP compare match event
DS310:8Data Selection MUX 3 Signal Selection bits
  • 0 CLCINA I/O pin
  • 1 CLC2 Out
  • 2 CMP2 out
  • 3 SPI2 SDO2 Out
  • 4 UART2 RX In
  • 5 SCCP4 OCM4 output
  • 6 SCCP4 OCMP compare match event
  • 7 SCCP5 OCMP compare match event
DS26:4Data Selection MUX 2 Signal Selection bits
  • 0 CLCINB I/O pin
  • 1 CLC1 out
  • 2 CMP1 out
  • 3 UART2 TX Out
  • 4 ADC End of Conversion
  • 5 DMA Channel 1 interrupt
  • 6 MCCP1 OCMP compare match event
  • 7 Unused
DS12:0Data Selection MUX 1 Signal Selection bits
  • 0 CLCINA I/O pin
  • 1 System Clock
  • 2 SOSC Clock
  • 3 LPRC Clock
  • 4 REFO1 Clock Output
  • 5 MCCP1 OCM1D Output
  • 6 MCCP1 OCM1E Output
  • 7 MCCP1 OCM1F Output

CLC2GLS

Address
0xBF802520
Reset
0x00000000
Access
read/write
Size
32-bit
32 fields
FieldBitsWhat it does
G4D4N30
G4D3T29
G4D3N28
G4D2T27
G4D2N26
G4D1T25
G4D1N24
G3D4T23
G3D4N22
G3D3T21
G3D3N20
G3D2T19
G3D2N18
G3D1T17
G3D1N16
G2D4T15
G2D4N14
G2D3T13
G2D3N12
G2D2T11
G2D2N10
G2D1T9
G2D1N8
G1D4T7
G1D4N6
G1D3T5
G1D3N4
G1D2T3
G1D2N2
G1D1T1
G1D1N0
G4D4T31