PIC32MM0064GPM048 CCP1 registers

The 9 registers of CCP1 (Capture/compare/PWM 1), from 0xBF800100, with their reset value and every field. The PIC32MM0064GPM048 has 433 registers in 53 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

CCP1 Capture/compare/PWM 1

CCP1CON1

Address
0xBF800100
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
FieldBitsWhat it does
RTRGEN30
OPS27:24
  • 0 Each time base period match or input capture event
  • 1 Every 2nd time base period match or 2nd input capture event
  • 2 Every 3rd time base period match or 3rd input capture event
  • 3 Every 4th time base period match or 4th input capture event
  • 4 Every 5th time base period match
  • 5 Every 6th time base period match
  • 6 Every 7th time base period match
  • 7 Every 8th time base period match
  • 8 Every 9th time base period match
  • 9 Every 10th time base period match
  • 10 Every 11th time base period match
  • 11 Every 12th time base period match
  • 12 Every 13th time base period match
  • 13 Every 14th time base period match
  • 14 Every 15th time base period match
  • 15 Every 16th time base period match
TRIGEN23
ONESHOT22
ALTSYNC21
SYNC20:16
  • 0 No external synchronization; timer rolls over at FFFFh or matches with the Timer Period register
  • 1 This MCCP/SCCP
  • 2 MCCP1
  • 3 MCCP2
  • 4 MCCP3
  • 9 INT0 pin
  • 10 INT1 pin
  • 11 INT2 pin
  • 12 INT3 pin
  • 13 INT4 pin
  • 14 SCCP8
  • 15 SCCP9
  • 16 CLC1
  • 17 CLC2
  • 18 CLC3
  • 19 CLC4
  • 24 Comparator 1
  • 25 Comparator 2
  • 26 Comparator 3
  • 27 Start of ADC conversion
  • 31 Off
ON15
SIDL13
CCPSLP12
TMRSYNC11
CLKSEL10:8
  • 0 System Clock (Fsys)
  • 1 REFCLKO Output Clock
  • 2 Secondary Oscillator Clock (SOSC)
  • 3 CLC1 Output
  • 4 Reserved
  • 5 Reserved
  • 6 TCKIB Pin (remappable)
  • 7 TCKIA Pin (remappable)
TMRPS7:6
  • 0 1:1 prescale
  • 1 1:4 prescale
  • 2 1:16 prescale
  • 3 1:64 prescale
T325
CCSEL4
MOD3:0
OPSSRC31

CCP1CON2

Address
0xBF800110
Reset
0x01000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
OCFEN29
OCEEN28
OCDEN27
OCCEN26
OCBEN25
OCAEN24
ICGSM23:22
AUXOUT20:19
ICS18:16
  • 0 ICM1 pin (remappable)
  • 1 Comparator 1 Output
  • 2 Comparator 2 Output
  • 3 Comparator 3 Output
  • 4 CLC1 Output
  • 5 CLC2 Output
  • 6 CLC3 Output
  • 7 CLC4 Output
PWMRSEN15
ASDGM14
  • 0 Shutdown event occurs immediately
  • 1 Waits until the next time base reset or rollover
SSDG12
ASDG7:0
  • 0 Disabled
  • 1 Comparator 1
  • 2 Comparator 2
  • 4 Comparator 3
  • 8 SCCP5 output
  • 16 SCCP4 output
  • 32 CLC1 output
  • 64 OCFA pin (remappable)
  • 128 OCFB pin (remappable)
OENSYNC31
  • 0 Update by output enable bits occurs immediately
  • 1 Update by output enable bits occurs on the next Time Base Reset or Rollover

CCP1CON3

Address
0xBF800120
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
OSCNT30:28
OUTM26:24
POLACE21
POLBDF20
PSSACE19:18
  • 0 Pins are in high impedance state
  • 2 Pins are driven inactive
  • 3 Pins are driven active
PSSBDF17:16
DT5:0
OETRIG31

CCP1STAT

Address
0xBF800130
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
PRLWIP20
TMRHWIP19
TMRLWIP18
RBWIP17
RAWIP16
ICGARM10
CCPTRIG7
TRSET6
TRCLR5
ASEVT4
SCEVT3
ICDIS2
ICOV1
ICBNE0

CCP1TMR

Address
0xBF800140
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
TMRL15:0
TMRH31:16

CCP1PR

Address
0xBF800150
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
PRL15:0
PRH31:16

CCP1RA

Address
0xBF800160
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CMPA15:0

CCP1RB

Address
0xBF800170
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CMPB15:0

CCP1BUF

Address
0xBF800180
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
BUFL15:0
BUFH31:16