The 30 registers of ADC (Analog-to-digital converter), from 0xBF802100, with their reset value and every field. The PIC32MM0128GPM048 has 433 registers in 53 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
ADC Analog-to-digital converter
ADC1BUF0
Address
0xBF802100
Reset
0x00000000
Access
read/write
Size
32-bit
ADC1BUF1
Address
0xBF802110
Reset
0x00000000
Access
read/write
Size
32-bit
ADC1BUF2
Address
0xBF802120
Reset
0x00000000
Access
read/write
Size
32-bit
ADC1BUF3
Address
0xBF802130
Reset
0x00000000
Access
read/write
Size
32-bit
ADC1BUF4
Address
0xBF802140
Reset
0x00000000
Access
read/write
Size
32-bit
ADC1BUF5
Address
0xBF802150
Reset
0x00000000
Access
read/write
Size
32-bit
ADC1BUF6
Address
0xBF802160
Reset
0x00000000
Access
read/write
Size
32-bit
ADC1BUF7
Address
0xBF802170
Reset
0x00000000
Access
read/write
Size
32-bit
ADC1BUF8
Address
0xBF802180
Reset
0x00000000
Access
read/write
Size
32-bit
ADC1BUF9
Address
0xBF802190
Reset
0x00000000
Access
read/write
Size
32-bit
ADC1BUF10
Address
0xBF8021A0
Reset
0x00000000
Access
read/write
Size
32-bit
ADC1BUF11
Address
0xBF8021B0
Reset
0x00000000
Access
read/write
Size
32-bit
ADC1BUF12
Address
0xBF8021C0
Reset
0x00000000
Access
read/write
Size
32-bit
ADC1BUF13
Address
0xBF8021D0
Reset
0x00000000
Access
read/write
Size
32-bit
ADC1BUF14
Address
0xBF8021E0
Reset
0x00000000
Access
read/write
Size
32-bit
ADC1BUF15
Address
0xBF8021F0
Reset
0x00000000
Access
read/write
Size
32-bit
ADC1BUF16
Address
0xBF802200
Reset
0x00000000
Access
read/write
Size
32-bit
ADC1BUF17
Address
0xBF802210
Reset
0x00000000
Access
read/write
Size
32-bit
ADC1BUF18
Address
0xBF802220
Reset
0x00000000
Access
read/write
Size
32-bit
ADC1BUF19
Address
0xBF802230
Reset
0x00000000
Access
read/write
Size
32-bit
ADC1BUF20
Address
0xBF802240
Reset
0x00000000
Access
read/write
Size
32-bit
ADC1BUF21
Address
0xBF802250
Reset
0x00000000
Access
read/write
Size
32-bit
AD1CON1ADC Control Register 1
Address
0xBF802260
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
ON
15
ADC Operating Mode bit
0 ADC module is not operating
1 ADC module is operating
SIDL
13
Stop in Idle Mode bit
0 Continue module operation in Idle mode
1 Discontinue module operation when device enters Idle mode
FORM
10:8
Data Output Format bits
0 Integer 16-bit
1 Signed Integer 16-bit
2 Fractional 16-bit
3 Signed Fractional 16-bit
4 Integer 32-bit
5 Signed Integer 32-bit
6 Fractional 32-bit
7 Signed Fractional 32-bit
SSRC
7:4
Conversion Trigger Source Select bits
0 Clearing SAMP bit ends sampling and starts conversion
1 Active transition on INT0 pin ends sampling and starts conversion
2 Timer 3 period match ends sampling and starts conversion
5 Timer1 period match ends sampling and starts conversion (will not trigger during Sleep mode)
6 Timer1 period match ends sampling and starts conversion (can trigger during Sleep mode)
7 Internal counter ends sampling and starts conversion (auto convert)
8 MCCP1 module event ends sampling and starts conversion
9 MCCP2 module event ends sampling and starts conversion
10 MCCP3 module event ends sampling and starts conversion
11 SCCP4 module event ends sampling and starts conversion
12 SCCP5 module event ends sampling and starts conversion
13 SCCP6 module event ends sampling and starts conversion
14 CLC1 module event ends sampling and starts conversion
15 CLC2 module event ends sampling and starts conversion
MODE12
3
ADC Operation Mode
0 10-bit ADC operation
1 12-bit ADC operation
ASAM
2
ADC Sample Auto-Start bit
0 Sampling begins when SAMP bit is set
1 Sampling begins immediately after last conversion completes; SAMP bit is automatically set.
SAMP
1
ADC Sample Enable bit
0 The ADC sample/hold amplifier is holding
1 The ADC sample and hold amplifier is sampling
DONE
0
Analog-to-Digital Conversion Status bit
0 Analog-to-digital conversion is not done or has not started
1 Analog-to-digital conversion is done
AD1CON2
Address
0xBF802270
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
VCFG
15:13
Voltage Reference Configuration bits
0 VREFH is AVDD and VREFL is AVSS
1 VREFH is AVDD and VREFL is External VREF- pin
2 VREFH is External VREF + pin and VREFL is AVSS
3 VREFH is External VREF+ pin and VREFL is External VREF- pin
OFFCAL
12
Input Offset Calibration Mode Select bit
0 Disable Offset Calibration mode; The inputs to the sample and hold amplifier are controlled by AD1CHS or AD1CSS
1 Enable Offset Calibration mode; Positive and negative inputs of the sample and hold amplifier are connected to negative reference
BUFREGEN
11
CSCNA
10
Input Scan Select bit
0 Do not scan inputs
1 Scan inputs
BUFS
7
Buffer Fill Status bit
0 ADC is currently filling buffer 0-10; user should access data in 11-21
1 ADC is currently filling buffer 11-21; user should access data in 0-10
SMPI
6:2
Sample/Convert Sequences Per Interrupt Selection bits
0 Interrupts at the completion of conversion for each sample/convert sequence
1 Interrupts at the completion of conversion for each 2nd sample/convert sequence
2 Interrupts at the completion of conversion for each 3rd sample/convert sequence
3 Interrupts at the completion of conversion for each 4th sample/convert sequence
4 Interrupts at the completion of conversion for each 5th sample/convert sequence
5 Interrupts at the completion of conversion for each 6th sample/convert sequence
6 Interrupts at the completion of conversion for each 7th sample/convert sequence
7 Interrupts at the completion of conversion for each 8th sample/convert sequence
8 Interrupts at the completion of conversion for each 9th sample/convert sequence
9 Interrupts at the completion of conversion for each 10th sample/convert sequence
10 Interrupts at the completion of conversion for each 11th sample/convert sequence
11 Interrupts at the completion of conversion for each 12th sample/convert sequence
12 Interrupts at the completion of conversion for each 13th sample/convert sequence
13 Interrupts at the completion of conversion for each 14th sample/convert sequence
14 Interrupts at the completion of conversion for each 15th sample/convert sequence
15 Interrupts at the completion of conversion for each 16th sample/convert sequence
BUFM
1
ADC Result Buffer Mode Select bit
0 Buffer configured as one 22-word buffer ADC1BUF21-ADC1BUF0
1 Buffer configured as two 11-word buffers ADC1BUF10-ADC1BUF0 / ADC1BUF21-ADCBUF11