The 2 registers of IC4 (Input capture 4), from 0xBF802600, with their reset value and every field. The PIC32MX170F512H has 458 registers in 53 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
IC4 Input capture 4
IC4CONInput Capture 1 Control Register
Address
0xBF802600
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
ON
15
Input Capture Module Enable bit
0 Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
1 Module is enabled
SIDL
13
Stop in Idle Control bit
0 Continue to operate in Idle mode
1 Halt in CPU Idle mode
FEDGE
9
First Capture Edge Select bit
0 Capture falling edge first
1 Capture rising edge first
C32
8
32-bit Capture Select bit
0 16-bit timer resource capture
1 32-bit timer resource capture
ICTMR
7
Timer Select bit
0 Timer3 is the counter source for capture
1 Timer2 is the counter source for capture
ICI
6:5
Interrupt Control bits
0 Interrupt on every capture event
1 Interrupt on every second capture event
2 Interrupt on every third capture event
3 Interrupt on every fourth capture event
ICOV
4
Input Capture Overflow Status Flag bit
0 No input capture overflow has occurred
1 Input capture overflow has occurred
ICBNE
3
Input Capture Buffer Not Empty Status bit
0 Input capture buffer is empty
1 Input capture buffer is not empty; at least one more capture value can be read
ICM
2:0
Input Capture Mode Select bits
0 Input Capture module is disabled
1 Edge Detect mode every edge (rising and falling)
2 Simple Capture Event mode every falling edge
3 Simple Capture Event mode every rising edge
4 Prescaled Capture Event mode every fourth rising edge
5 Prescaled Capture Event mode every sixteenth rising edge
6 Simple Capture Event mode every edge, specified edge first and every edge thereafter
7 Interrupt-Only mode (only supported while in Sleep mode or Idle mode)
BETA