The 3 registers of TMR1 (Timer 1), from 0xBF800600, with their reset value and every field. The PIC32MX170F512H has 458 registers in 53 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
TMR1 Timer 1
T1CONTYPE A TIMER CONTROL REGISTER
Address
0xBF800600
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
ON
15
Timer On bit
0 Timer is disabled
1 Timer is enabled
SIDL
13
Stop in Idle Mode bit
0 Continue operation even in Idle mode
1 Discontinue operation when device enters Idle mode
TWDIS
12
Asynchronous Timer Write Disable bit
0 Back-to-back writes are enabled (Legacy Asynchronous Timer functionality)
1 Writes to TMR1 are ignored until pending write operation completes
TWIP
11
Asynchronous Timer Write in Progress bit
0 (In Asynchronous Timer mode) Asynchronous write to TMR1 register complete / (in synchronous mode) read as 0
1 (In Asynchronous Timer mode) Asynchronous write to TMR1 register in progress / (in synchronous mode) read as 0
TGATE
7
Timer Gated Time Accumulation Enable bit
0 (When TCS is 0) Gated time accumulation is disabled / (When TCS is 1) bit is ignored
1 (When TCS is 0) Gated time accumulation is enabled / (When TCS is 1) bit is ignored
TCKPS
5:4
Timer Input Clock Prescale Select bits
0 1:1 prescale value
1 1:8 prescale value
2 1:64 prescale value
3 1:256 prescale value
TSYNC
2
Timer External Clock Input Synchronization Selection bit
0 (When TCS is 1) External clock input is not synchronized / (When TCS is 0) bit is ignored
1 (When TCS is 1) External clock input is synchronized / (When TCS is 0) bit is ignored
BETA