The 4 registers of OSC (Oscillator and clocks), from 0xBF80F000, with their reset value and every field. The PIC32MX170F512L has 478 registers in 56 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
OSC Oscillator and clocks
OSCCONOscillator Control Register
Address
0xBF80F000
Reset
0x00200007
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
PLLODIV
29:27
Output Divider for PLL
0 PLL output divided by 1
1 PLL output divided by 2
2 PLL output divided by 4
3 PLL output divided by 8
4 PLL output divided by 16
5 PLL output divided by 32
6 PLL output divided by 64
7 PLL output divided by 256
FRCDIV
26:24
Internal Fast RC Oscillator Clock Divider bits
0 FRC divided by 1
1 FRC divided by 2 (default setting)
2 FRC divided by 4
3 FRC divided by 8
4 FRC divided by 16
5 FRC divided by 32
6 FRC divided by 64
7 FRC divided by 256
SOSCRDY
22
Secondary Oscillator (SOSC) Ready Indicator bit
0 Secondary Oscillator is still warming up or is turned off
1 Indicates that the Secondary Oscillator is running and is stable
PBDIVRDY
21
Peripheral Bus Clock Divisor Ready bit
0 PBDIV(1:0) bits cannot be written
1 PBDIV(1:0) bits can be written
PBDIV
20:19
Peripheral Bus Clock (PBCLK) Divisor bits
0 PBCLK is SYSCLK divided by 1
1 PBCLK is SYSCLK divided by 2
2 PBCLK is SYSCLK divided by 4
3 PBCLK is SYSCLK divided by 8 (default)
PLLMULT
18:16
Phase-Locked Loop (PLL) Multiplier bits
0 Clock is multiplied by 15
1 Clock is multiplied by 16
2 Clock is multiplied by 17
3 Clock is multiplied by 18
4 Clock is multiplied by 19
5 Clock is multiplied by 20
6 Clock is multiplied by 21
7 Clock is multiplied by 24
COSC
14:12
Current Oscillator Selection bits
0 Internal Fast RC (FRC) Oscillator
1 Internal Fast RC Oscillator with PLL module via Postscaler (FRCPLL)
2 Primary Oscillator (POSC) (XT/HS/EC)
3 Primary Oscillator (POSC) with PLL module (XTPLL/HSPLL/ECPLL)
4 Secondary Oscillator (SOSC)
5 Internal Low-Power RC (LPRC) Oscillator
6 Internal Fast RC (FRC) Oscillator divided by 16
7 Internal Fast RC (FRC) Oscillator divided by OSCCON(FRCDIV) bits
NOSC
10:8
New Oscillator Selection bits
0 Internal Fast Internal RC Oscillator (FRC)
1 Internal Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL)
2 Primary Oscillator (XT/HS/EC)
3 Primary Oscillator with PLL module (XTPLL/HSPLL/ECPLL)
4 Secondary Oscillator (SOSC)
5 Internal Low-Power RC (LPRC) Oscillator
6 Internal Fast RC Oscillator (FRC) divided by 16
7 Internal Fast RC Oscillator (FRC) divided by OSCCON(FRCDIV) bits
CLKLOCK
7
Clock Selection Lock Enable bit
0 (If FCKSM(1:0) is 1x) Clock and PLL selections are not locked and may be modified / (If FCKSM(1:0) is 0x) Clock and PLL selections are never locked and may be modified
1 (If FCKSM(1:0) is 1x) Clock and PLL selections are locked / (If FCKSM(1:0) is 0x) Clock and PLL selections are never locked and may be modified
ULOCK
6
SLOCK
5
PLL Lock Status bit
0 PLL module is out of lock
1 PLL module is in lock or PLL module start-up timer is satisfied
SLPEN
4
Sleep Mode Enable bit
0 Device will enter Idle mode when a WAIT instruction is executed
1 Device will enter Sleep mode when a WAIT instruction is executed
CF
3
Clock Fail Detect bit
0 No clock failure has been detected
1 FSCM has detected a clock failure
UFRCEN
2
SOSCEN
1
Secondary Oscillator Enable bit
0 Disable Secondary Oscillator
1 Enable Secondary Oscillator
OSWEN
0
Oscillator Switch Enable bit
0 Oscillator switch is complete
1 Initiate an oscillator switch to selection specified by NOSC(2:0) bits
OSCTUNFRC Tuning Register
Address
0xBF80F010
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TUN
5:0
FRC Oscillator Tuning bits
0 Center frequency. Oscillator runs at minimal frequency (8 MHz)
31 Center frequency + 1.5%
32 Center frequency - 1.5%
REFOCONReference Oscillator Control Register
Address
0xBF80F020
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
RODIV
30:16
Reference Clock Divider bits
0 Reference Clock output is same as source clock
1 Reference Clock output is source clock divided by 2
2 Reference Clock output is source clock divided by 4
32767 Reference Clock output is source clock divided by 65534
ON
15
Output Enable bit
0 Reference Oscillator Module is disabled
1 Reference Oscillator Module is enabled
SIDL
13
Peripheral Stop in Idle Mode bit
0 Continue module operation in Idle mode
1 Discontinue module operation when device enters Idle mode
OE
12
Reference Clock Output Enable bit
0 Reference clock is not driven out on REFCLKO pin
1 Reference clock is driven out on REFCLKO pin
RSLP
11
Reference Oscillator Module Run in Sleep bit
0 Reference Oscillator Module output is disabled in Sleep
1 Reference Oscillator Module output continues to run in Sleep
BETA