PIC32MX250F256L CFG registers

The 3 registers of CFG (Configuration and pin control), from 0xBF80F200, with their reset value and every field. The PIC32MX250F256L has 514 registers in 57 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

CFG Configuration and pin control

CFGCONConfiguration Control Register

Address
0xBF80F200
Reset
0x00000008
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
IOLOCK13Peripheral Pin Select Lock bit
  • 0 Peripheral Pin Select is not locked. Writes to PPS registers is allowed.
  • 1 Peripheral Pin Select is locked. Writes to PPS registers is not allowed.
PMDLOCK12Peripheral Module Disable bit
  • 0 Peripheral module is not locked. Writes to PMD registers is allowed.
  • 1 Peripheral module is locked. Writes to PMD registers is not allowed.
JTAGEN3JTAG Port Enable bit
  • 0 Disable the JTAG port
  • 1 Enable the JTAG port
TROEN2
TDOEN0TDO Enable for 2-Wire JTAG bit
  • 0 2-wire JTAG protocol does not use TDO
  • 1 2-wire JTAG protocol uses TDO

DEVIDDevice and Revision ID Register

Address
0xBF80F220
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
VER28
DEVID27:0

SYSKEY

Address
0xBF80F230
Reset
0x00000000
Access
read only
Size
32-bit