The 22 registers of INT (Interrupt controller), from 0xBF881000, with their reset value and every field. The PIC32MX270F512H has 494 registers in 54 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
INT Interrupt controller
INTCONInterrupt Control Register
Address
0xBF881000
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
SS0
16
MVEC
12
Multi Vector Configuration bit
0 Interrupt controller configured for single vectored mode
1 Interrupt controller configured for multi vectored mode
TPC
10:8
Interrupt Proximity Timer Control bits
0 Disables Interrupt Proximity timer
1 Interrupts of group priority 1 start the Interrupt Proximity timer
2 Interrupts of group priority 2 or lower start the Interrupt Proximity timer
3 Interrupts of group priority 3 or lower start the Interrupt Proximity timer
4 Interrupts of group priority 4 or lower start the Interrupt Proximity timer
5 Interrupts of group priority 5 or lower start the Interrupt Proximity timer
6 Interrupts of group priority 6 or lower start the Interrupt Proximity timer
7 Interrupts of group priority 7 or lower start the Interrupt Proximity timer
INT4EP
4
External Interrupt 4 Edge
0 Falling edge
1 Rising edge
INT3EP
3
External Interrupt 3 Edge
0 Falling edge
1 Rising edge
INT2EP
2
External Interrupt 2 Edge
0 Falling edge
1 Rising edge
INT1EP
1
External Interrupt 1 Edge
0 Falling edge
1 Rising edge
INT0EP
0
External Interrupt 0 Edge
0 Falling edge
1 Rising edge
INTSTATInterrupt Status Register
Address
0xBF881010
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
SRIPL
10:8
Requested Priority Level bits
0 Priority level 0 of the latest interrupt presented to the CPU
1 Priority level 1 of the latest interrupt presented to the CPU
2 Priority level 2 of the latest interrupt presented to the CPU
3 Priority level 3 of the latest interrupt presented to the CPU
4 Priority level 4 of the latest interrupt presented to the CPU
5 Priority level 5 of the latest interrupt presented to the CPU
6 Priority level 6 of the latest interrupt presented to the CPU
7 Priority level 7 of the latest interrupt presented to the CPU
BETA