The 5 registers of NVM (Flash controller (NVM)), from 0xBF80F400, with their reset value and every field. The PIC32MX270F512H has 494 registers in 54 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
NVM Flash controller (NVM)
NVMCONProgramming Control Register
Address
0xBF80F400
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
WR
15
Write Control bit
0 Flash operation complete or inactive
1 Initiate a Flash operation. Hardware clears this bit when the operation completes
WREN
14
Write Enable bit
0 Disable writes to WR bit and disables LVD circuit
1 Enable writes to WR bit and enables LVD circuit
WRERR
13
Write Error bit
0 Program or erase sequence completed normally
1 Program or erase sequence did not complete successfully
LVDERR
12
Low-Voltage Detect Error bit
0 Voltage level is acceptable for programming
1 Low-voltage detected (possible data corruption if WRERR is set)
LVDSTAT
11
Low-Voltage Detect Status bit
0 Low-voltage event NOT active
1 Low-voltage event active
NVMOP
3:0
NVM Operation bits
0 No operation
1 Word program operation: programs word selected by NVMADDR if it is not write-protected
2 No operation
3 Row program operation: programs row selected by NVMADDR if it is not write-protected
4 Page erase operation: erases page selected by NVMADDR if it is not write-protected
5 Program Flash (PFM) erase operation: erases PFM if all pages are not write-protected
BETA