PIC32MX430F064L PMP registers

The 7 registers of PMP (Parallel master port), from 0xBF807000, with their reset value and every field. The PIC32MX430F064L has 431 registers in 55 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

PMP Parallel master port

PMCONParallel Port Control Register

Address
0xBF807000
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
ON15Parallel Master Port Enable bit
  • 0 PMP is disabled
  • 1 PMP is enabled
SIDL13Stop in Idle Mode bit
  • 0 Continue module operation in Idle mode
  • 1 Discontinue module operation when device enters Idle mode
ADRMUX12:11Address/Data Multiplexing Selection bits
  • 0 Address and data appear on separate pins
  • 1 Lower 8 bits of address are multiplexed on PMD(7:0) pins
  • 2 All 16 bits of address are multiplexed on PMD(7:0) pins
  • 3 Lower 8 bits of address are multiplexed on PMD(15:0) pins
PMPTTL10PMP Module TTL Input Buffer Select bit
  • 0 PMP module uses Schmitt Trigger input buffer
  • 1 PMP module uses TTL input buffers
PTWREN9Write Enable Strobe Port Enable bit
  • 0 PMWR/PMENB port is disabled
  • 1 PMWR/PMENB port is enabled
PTRDEN8Read/Write Strobe Port Enable bit
  • 0 PMRD/PMWR port is disabled
  • 1 PMRD/PMWR port is enabled
CSF7:6Chip Select Function bits
  • 0 PMCS1 and PMCS2 function as address bits 14 and 15
  • 1 PMCS1 functions as address bit 14; PMCS2 functions as Chip Select
  • 2 PMCS1 and PMCS2 function as Chip Select
  • 3 Reserved
ALP5Address Latch Polarity bit
  • 0 Active-low (PMALL and PMALH)
  • 1 Active-high (PMALL and PMALH)
CS2P4Chip Select 0 Polarity bit
  • 0 Active-low (PMCS2)
  • 1 Active-high (PMCS2)
CS1P3Chip Select 0 Polarity bit
  • 0 Active-low (PMCS1)
  • 1 Active-high (PMCS1)
WRSP1Write Strobe Polarity bit
  • 0 (If MODE(1:0) = 00/01/10) Write strobe active-low / (If MODE(1:0) = 11) Enable strobe active-low
  • 1 (If MODE(1:0) = 00/01/10) Write strobe active-high / (If MODE(1:0) = 11) Enable strobe active-high
RDSP0Read Strobe Polarity bit
  • 0 (If MODE(1:0) = 00/01/10) Read Strobe active-low / (If MODE(1:0) = 11) Read/write strobe active-low
  • 1 (If MODE(1:0) = 00/01/10) Read Strobe active-high / (If MODE(1:0) = 11) Read/write strobe active-high

PMMODEParallel Port Mode Register

Address
0xBF807010
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
BUSY15Busy bit (Master mode only)
  • 0 Port is not busy
  • 1 Port is busy
IRQM14:13Interrupt Request Mode bits
  • 0 No Interrupt generated
  • 1 Interrupt generated at the end of the read/write cycle
  • 2 Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA(1:0) =11 (Addressable Slave mode only)
  • 3 Reserved
INCM12:11Increment Mode bits
  • 0 No increment or decrement of address
  • 1 Increment ADDR(15:0) by 1 every read/write cycle
  • 2 Decrement ADDR(15:0) by 1 every read/write cycle
  • 3 Slave mode read and write buffers auto-increment (MODE(1:0) = 00 only)
MODE16108/16-bit Mode bit
  • 0 8-bit mode: a read or write to the data register invokes a single 8-bit transfer
  • 1 16-bit mode: a read or write to the data register invokes a single 16-bit transfer
MODE9:8Parallel Port Mode Select bits
  • 0 Legacy Parallel Slave Port
  • 1 Enhanced Slave mode
  • 2 Master mode 2 (PMCSx
  • 3 Master mode 1 (PMCSx
WAITB7:6Data Setup to Read/Write Strobe Wait States bits
  • 0 Data wait of 1 TPB; multiplexed address phase of 1 TPB (default)
  • 1 Data wait of 2 TPB; multiplexed address phase of 2 TPB
  • 2 Data wait of 3 TPB; multiplexed address phase of 3 TPB
  • 3 Data wait of 4 TPB; multiplexed address phase of 4 TPB
WAITM5:2Data Read/Write Strobe Wait States bits
  • 0 Wait of 1TPB (default)
  • 1 Wait of 2TPB
  • 2 Wait of 3TPB
  • 3 Wait of 4TPB
  • 4 Wait of 5TPB
  • 5 Wait of 6TPB
  • 6 Wait of 7TPB
  • 7 Wait of 8TPB
  • 8 Wait of 9TPB
  • 9 Wait of 10TPB
  • 10 Wait of 11TPB
  • 11 Wait of 12TPB
  • 12 Wait of 13TPB
  • 13 Wait of 14TPB
  • 14 Wait of 15TPB
  • 15 Wait of 16TPB
WAITE1:0Data Hold After Read/Write Strobe Wait States bits
  • 0 (for write operations) Wait of 1 TPB (default) / (for read operations) Wait of 0 TPB (default)
  • 1 (for write operations) Wait of 2 TPB / (for read operations) Wait of 1 TPB
  • 2 (for write operations) Wait of 3 TPB / (for read operations) Wait of 2 TPB
  • 3 (for write operations) Wait of 4 TPB / (for read operations) Wait of 3 TPB

PMADDRParallel Port Address Register

Address
0xBF807020
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
CS14
ADDR13:0Address bits
  • 0 address is 0
  • 16383 address is 0x3fff

PMDOUT

Address
0xBF807030
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATAOUT31:0

PMDIN

Address
0xBF807040
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATAIN31:0

PMAENParallel Port Pin Enable Register

Address
0xBF807050
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PTEN15:0PMALH/PMALL Port Enable bits
  • 0 PMA1 and PMA0 pads function as port I/O
  • 3 PMA1 and PMA0 function as either PMA(1:0) or PMALH and PMALL

PMSTATParallel Port Status Register (Slave modes only)

Address
0xBF807060
Reset
0x0000008F
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
IBF15Input Buffer Full Status bit
  • 0 Some or all of the writable input buffer registers are empty
  • 1 All writable input buffer registers are full
IBOV14Input Buffer Overflow Status bit
  • 0 No overflow occurred
  • 1 A write attempt to a full input byte buffer occurred (must be cleared in software)
IB3F11
IB2F10
IB1F9
IB0F8
OBE7Output Buffer Empty Status bit
  • 0 Some or all of the readable output buffer registers are full
  • 1 All readable output buffer registers are empty
OBUF6Output Buffer Underflow Status bit
  • 0 No underflow occurred
  • 1 A read occurred from an empty output byte buffer (must be cleared in software)
OB3E3
OB2E2
OB1E1
OB0E0