The 8 registers of BMX (Bus matrix), from 0xBF882000, with their reset value and every field. The PIC32MX450F256L has 431 registers in 55 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
BMX Bus matrix
BMXCONBus Matrix Configuration Register
Address
0xBF882000
Reset
0x001F0041
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
BMXCHEDMA
26
BMX PFM Cacheability for DMA Accesses bit
0 Disable program Flash memory (data) cacheability for DMA accesses(hits are still read from the cache
1 Enable program Flash memory (data) cacheability for DMA accesses (requires cache to have data caching enabled)
BMXERRIXI
20
Enable Bus Error from IXI bit
0 Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus
1 Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus
BMXERRICD
19
Enable Bus Error from ICD Debug Unit bit
0 Disable bus error exceptions for unmapped address accesses initiated from ICD
1 Enable bus error exceptions for unmapped address accesses initiated from ICD
BMXERRDMA
18
Bus Error from DMA bit
0 Disable bus error exceptions for unmapped address accesses initiated from DMA
1 Enable bus error exceptions for unmapped address accesses initiated from DMA
BMXERRDS
17
Bus Error from CPU Data Access bit
0 Disable bus error exceptions for unmapped address accesses initiated from CPU data access
1 Enable bus error exceptions for unmapped address accesses initiated from CPU data access
BMXERRIS
16
Bus Error from CPU Instruction Access bit
0 Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access
1 Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access
BMXWSDRM
6
CPU Instruction or Data Access from Data RAM Wait State bit
0 Data RAM accesses from CPU have zero wait states for address setup
1 Data RAM accesses from CPU have one wait state for address setup
BMXARB
2:0
Bus Matrix Arbitration Mode bits
0 Arbitration Mode 0
1 Arbitration Mode 1 (default)
2 Arbitration Mode 2
3 Reserved (using these configuration modes will produce undefined behavior)
4 Reserved (using these configuration modes will produce undefined behavior)
5 Reserved (using these configuration modes will produce undefined behavior)
6 Reserved (using these configuration modes will produce undefined behavior)
7 Reserved (using these configuration modes will produce undefined behavior)
BMXDKPBAData RAM Kernel Program Base Address Register
Address
0xBF882010
Reset
0x00000000
Access
read/write
Size
32-bit
BMXDUDBAData RAM User Data Base Address Register
Address
0xBF882020
Reset
0x00000000
Access
read/write
Size
32-bit
BMXDUPBAData RAM User Program Base Address Register
Address
0xBF882030
Reset
0x00000000
Access
read/write
Size
32-bit
BMXDRMSZData RAM Size Register
Address
0xBF882040
Reset
0x00020000
Access
read only
Size
32-bit
BMXPUPBAProgram Flash (PFM) User Program Base Address Register
BETA