The 6 registers of DMAC (DMA controller), from 0xBF883000, with their reset value and every field. The PIC32MX550F256L has 695 registers in 58 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
DMAC DMA controller
DMACONDMA Controller Control Register
Address
0xBF883000
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
ON
15
DMA On bit
0 DMA module is enabled
0 DMA module is disabled
SUSPEND
12
DMA Suspend bit
0 DMA operates normally
1 DMA transfers are suspended to allow CPU uninterrupted access to data bus
DMABUSY
11
DMA Module Busy bit
0 DMA module is disabled and not actively transferring data
1 DMA module is active
DMASTATDMA Status Register
Address
0xBF883010
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
RDWR
3
Read/Write Status bit
0 Last DMA bus access was a write
1 Last DMA bus access was a read
DMACH
1:0
DMAADDRDMA Address Register
Address
0xBF883020
Reset
0x00000000
Access
read only
Size
32-bit
DCRCCONDMA CRC Control Register
Address
0xBF883030
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
BYTO
29:28
CRC Byte Order Selection bits
0 No swapping (i.e. source byte order)
1 Endian byte swap on word boundaries (i.e. reverse source byte order)
2 Swap half-words on word boundaries (i.e. reverse source half-word order with source byte order per half-word)
3 Endian byte swap on half-word boundaries (i.e. source half-word order with reverse source byte order per half-word)
WBO
27
CRC Write Byte Order Selection bit
0 Source data is written to the destination unaltered
1 Source data is written to the destination re-ordered as defined by BYTO
BITO
24
CRC Bit Order Selection bit
0 (When CRCTYP is 1) The IP header checksum is calculated Most Significant bit (MSb) first (i.e. not reflected) / (When CRCTYP is 0) The LFSR CRC is calculated Most Significant bit first (i.e. not reflected)
1 (When CRCTYP is 1) The IP header checksum is calculated Least Significant bit (LSb) first (i.e. reflected) / (When CRCTYP is 0) The LFSR CRC is calculated Least Significant bit first (i.e. reflected)
PLEN
12:8
Polynomial Length bits
1 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 0
2 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 1
3 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 2
4 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 3
5 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 4
6 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 5
7 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 6
8 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 7
9 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 8
10 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 9
11 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 10
12 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 11
13 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 12
14 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 13
15 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 14
16 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 15
17 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 16
18 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 17
19 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 18
20 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 19
21 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 20
22 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 21
23 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 22
24 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 23
25 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 24
26 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 25
27 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 26
28 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 27
29 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 28
30 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 29
31 (When CRCTYP=1) These bits are unused / (When CRCTYP=0) Polynomial length is 30
CRCEN
7
CRC Enable bit
0 CRC module is disabled and channel transfers proceed normally
1 CRC module is enabled and channel transfers are routed through the CRC module
CRCAPP
6
CRC Append Mode bit
0 The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the destination
1 The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer completes the DMA writes the calculated CRC value to the location given by CHxDSA
CRCTYP
5
CRC Type Selection bit
0 The CRC module will calculate a LFSR CRC
1 The CRC module will calculate an IP header checksum
BETA