PIC32MX564F064L OC5 registers

The 3 registers of OC5 (Output compare 5), from 0xBF803800, with their reset value and every field. The PIC32MX564F064L has 521 registers in 61 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

OC5 Output compare 5

OC5CONOutput Compare 'x' Control Register

Address
0xBF803800
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
ON15Output Compare Peripheral On bit
  • 0 Output Compare peripheral is disabled
  • 1 Output Compare peripheral is enabled
SIDL13Stop in Idle Mode bit
  • 0 Continue operation in Idle mode
  • 1 Discontinue operation when CPU enters Idle mode
OC32532-bit Compare Mode bit
  • 0 OCxR(15-0) and OCxRS(15-0) are used for comparisons to the 16-bit timer source
  • 1 OCxR(31-0) and/or OCxRS(31-0) are used for comparisions to the 32-bit timer source
OCFLT4PWM Fault Condition Status bit
  • 0 No PWM Fault condition has occurred
  • 1 PWM Fault condition has occurred (cleared in HW only)
OCTSEL3Output Compare Timer Select bit
  • 0 Timer2 is the clock source for this Output Compare module
  • 1 Timer3 is the clock source for this Output Compare module
OCM2:0Output Compare Mode Select bits
  • 0 Output compare peripheral is disabled but continues to draw current
  • 1 Initialize OCx pin low; compare event forces OCx pin high
  • 2 Initialize OCx pin high; compare event forces OCx pin low
  • 3 Compare event toggles OCx pin
  • 4 Initialize OCx pin low: generate single output pulse on OCx pin
  • 5 Initialize OCx pin low; generate continious output pulses on OCx pin
  • 6 PWM mode on OCx; Fault pin disabled
  • 7 PWM mode on OCx; Fault pin enabled

OC5R

Address
0xBF803810
Reset
0x00000000
Access
read/write
Size
32-bit

OC5RS

Address
0xBF803820
Reset
0x00000000
Access
read/write
Size
32-bit