The 5 registers of UART2 (UART 2), from 0xBF806800, with their reset value and every field. The PIC32MX564F128H has 506 registers in 58 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
UART2 UART 2
U2MODEUARTx Mode Register
Address
0xBF806800
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
ON
15
UARTx Enable bit
0 UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx registers; UARTx power consumption is minimal
1 UARTx is enabled. UARTx pins are controlled by UARTx as defined by UEN and UTXEN control bits
SIDL
13
Stop in Idle Mode bit
0 Continue operation in Idle mode
1 Discontinue operation when device enters Idle mode
IREN
12
IrDA Encoder and Decoder Enable bit
0 IrDA is disabled
1 IrDA is enabled
RTSMD
11
Mode Selection for UxRTS Pin bit
0 UxRTS pin is in Flow Control mode
1 UxRTS pin is in Simplex mode
UEN
9:8
UARTx Enable bits
0 UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by corresponding bits in the PORTx register
1 UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register
2 UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
3 UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register
WAKE
7
Enable Wake-up on Start bit Detect During Sleep Mode bit
0 Wake-up is disabled
1 Wake-up is enabled
LPBACK
6
UARTx Loopback Mode Select bit
0 Loopback mode is disabled
1 Loopback mode is enabled
ABAUD
5
Auto-Baud Enable bit
0 Baud rate measurement is disabled or completed
1 Enable baud rate measurement on the next character requires reception of Sync character (0x55); cleared by hardware upon completion
RXINV
4
Receive Polarity Inversion bit
0 UxRX Idle state is 1
1 UxRX Idle state is 0
BRGH
3
High Baud Rate Enable bit
0 Standard Speed mode 16x baud clock enabled
1 High-Speed mode 4x baud clock enabled
PDSEL
2:1
Parity and Data Selection bits
0 8-bit data no parity
1 8-bit data even parity
2 8-bit data odd parity
3 9-bit data no parity
STSEL
0
Stop Selection bit
0 1 Stop bit
1 2 Stop bits
U2STAUARTx Status and Control Register
Address
0xBF806810
Reset
0x00000110
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
ADM_EN
24
Automatic Address Detect Mode Enable bit
0 Automatic Address Detect mode is disabled
1 Automatic Address Detect mode is enabled
ADDR
23:16
UTXISEL
15:14
TX Interrupt Mode Selection bits
0 Interrupt is generated and asserted while the transmit buffer contains at least one empty space
1 Interrupt is generated and asserted when all characters have been transmitted
2 Interrupt is generated and asserted while the transmit buffer is empty
3 Reserved
UTXINV
13
Transmit Polarity Inversion bit
0 (If IrDA mode is disabled) UxTX Idle state is 1 / (If IrDA mode is enabled) IrDA encoded UxTX Idle state is 0
1 (If IrDA mode is disabled) UxTX Idle state is 0 / (If IrDA mode is enabled) IrDA encoded UxTX Idle state is 1
URXEN
12
Receiver Enable bit
0 UARTx receiver is disabled. UxRX pin is ignored by the UARTx module. UxRX pin is controlled by the port.
1 UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1)
UTXBRK
11
Transmit Break bit
0 Break transmission is disabled or completed
1 Send Break on next transmission. Start bit followed by twelve 0 bits, followed by Stop bit; cleared by hardware upon completion
UTXEN
10
Transmit Enable bit
0 UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset. UxTX pin is controlled by the port.
1 UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1)
UTXBF
9
Transmit Buffer Full Status bit (read-only)
0 Transmit buffer is not full, at least one more character can be written
1 Transmit buffer is full
TRMT
8
Transmit Shift Register is Empty bit (read-only)
0 Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer
1 Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)
URXISEL
7:6
Receive Interrupt Mode Selection bit
0 Interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least 1 data character)
1 Interrupt flag bit is asserted while receive buffer is 1/2 or more full (i.e., has 4 or more data characters)
2 Interrupt flag bit is asserted while receive buffer is 3/4 or more full (i.e., has 6 or more data characters)
3 Reserved
ADDEN
5
Address Character Detect bit
0 Address Detect mode is disabled
1 Address Detect mode is enabled. If 9-bit mode is not selected
RIDLE
4
Receiver Idle bit
0 Data is being received
1 Receiver is Idle
PERR
3
Parity Error Status bit
0 Parity error has not been detected
1 Parity error has been detected for the current character
FERR
2
Framing Error Status bit
0 Framing error has not been detected
1 Framing error has been detected for the current character
OERR
1
Receive Buffer Overrun Error Status bit.
0 Receive buffer has not overflowed
1 Receive buffer has overflowed
URXDA
0
Receive Buffer Data Available bit (read-only)
0 Receive buffer is empty
1 Receive buffer has data, at least one more character can be read
BETA