The 12 registers of PCACHE (Prefetch cache), from 0xBF884000, with their reset value and every field. The PIC32MX575F256H has 554 registers in 62 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
PCACHE Prefetch cache
CHECONCache Control Register
Address
0xBF884000
Reset
0x00000007
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
CHECOH
16
Cache Coherency Setting on a PFM Program Cycle bit
0 Invalidate all data lines and instruction lines that are not locked
1 Invalidate all data and instruction lines
DCSZ
9:8
Data Cache Size in Lines bits
0 Disable data caching
1 Enable data caching with a size of 1 Line
2 Enable data caching with a size of 2 Lines
3 Enable data caching with a size of 4 Lines
PREFEN
5:4
Predictive Prefetch Enable bits
0 Disable predictive prefetch
1 Enable predictive prefetch for cacheable regions only
2 Enable predictive prefetch for non-cacheable regions only
3 Enable predictive prefetch for both cacheable and non-cacheable regions
PFMWS
2:0
PFM Access Time Defined in Terms of SYSLK Wait States bits
0 Zero Wait state
1 One Wait state
2 Two Wait states
3 Three Wait states
4 Four Wait states
5 Five Wait states
6 Six Wait states
7 Seven Wait states
CHEACCCache Access Register
Address
0xBF884010
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
CHEIDX
3:0
Cache Line Index bits
0 Select cache line 0 for reading or writing
1 Select cache line 1 for reading or writing
2 Select cache line 2 for reading or writing
3 Select cache line 3 for reading or writing
4 Select cache line 4 for reading or writing
5 Select cache line 5 for reading or writing
6 Select cache line 6 for reading or writing
7 Select cache line 7 for reading or writing
8 Select cache line 8 for reading or writing
9 Select cache line 9 for reading or writing
10 Select cache line 10 for reading or writing
11 Select cache line 11 for reading or writing
12 Select cache line 12 for reading or writing
13 Select cache line 13 for reading or writing
14 Select cache line 14 for reading or writing
15 Select cache line 15 for reading or writing
CHEWEN
31
Cache Access Enable bits for registers CHETAG
0 The cache line selected by CHEIDX(3:0) is not writeable
1 The cache line selected by CHEIDX(3:0) is writeable
CHETAGCache TAG Register
Address
0xBF884020
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
LTAG
4
LVALID
3
Line Valid bit
0 The line is not valid and is not compared to the physical address for hit detection
1 The line is valid and is compared to the physical address for hit detection
LLOCK
2
Line Lock bit
0 The line is not locked and can be replaced
1 The line is locked and will not be replaced
LTYPE
1
Line Type bit
0 The line caches data words
1 The line caches instruction words
LTAGBOOT
31
Line TAG Address Boot bit
0 The line is in the 0x1FC00000 (physical) area of memory
1 The line is in the 0x1D000000 (physical) area of memory
CHEMSKCache TAG Mask Register
Address
0xBF884030
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
LMASK
15:5
Line Mask bits
0 Only writeable for values of CHEIDX(3:0) bits (CHEACC(3:0)) equal to 0x0A and 0x0B. Disables mask logic.
1 Enables mask logic to force a match on the corresponding bit position in the LTAG(19:0) bits (CHETAG(23:4)) and the physical address.
BETA