The 22 registers of ADC (Analog-to-digital converter), from 0xBF809000, with their reset value and every field. The PIC32MX575F512L has 569 registers in 65 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
ADC Analog-to-digital converter
AD1CON1ADC Control Register 1
Address
0xBF809000
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
ON
15
ADC Operating Mode bit
0 ADC module is not operating
1 ADC module is operating
SIDL
13
Stop in Idle Mode bit
0 Continue module operation in Idle mode
1 Discontinue module operation when device enters Idle mode
FORM
10:8
Data Output Format bits
0 Integer 16-bit
1 Signed Integer 16-bit
2 Fractional 16-bit
3 Signed Fractional 16-bit
4 Integer 32-bit
5 Signed Integer 32-bit
6 Fractional 32-bit
7 Signed Fractional 32-bit
SSRC
7:5
Conversion Trigger Source Select bits
0 Clearing SAMP bit ends sampling and starts conversion
1 Active transition on INT0 pin ends sampling and starts conversion
2 Timer 3 period match ends sampling and starts conversion
3 Reserved
4 Reserved
5 Reserved
6 Reserved
7 Internal counter ends sampling and starts conversion (auto convert)
CLRASAM
4
Stop Conversion Sequence bit (when the first ADC interrupt is generated)
0 Normal operation, buffer contents will be overwritten by the next conversion sequence
1 Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the ADC interrupt is generated.
ASAM
2
ADC Sample Auto-Start bit
0 Sampling begins when SAMP bit is set
1 Sampling begins immediately after last conversion completes; SAMP bit is automatically set.
SAMP
1
ADC Sample Enable bit
0 The ADC sample/hold amplifier is holding
1 The ADC sample and hold amplifier is sampling
DONE
0
Analog-to-Digital Conversion Status bit
0 Analog-to-digital conversion is not done or has not started
1 Analog-to-digital conversion is done
AD1CON2ADC Control Register 2
Address
0xBF809010
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
VCFG
15:13
Voltage Reference Configuration bits
0 VREFH is AVDD and VREFL is AVSS
1 VREFH is Ext VREF + pin and VREFL is AVSS
2 VREFH is AVDD and VREFL is External VREF- pin
3 VREFH is External VREF+ pin and VREFL is External VREF- pin
4 VREFH is AVDD and VREFL is AVSS
5 VREFH is AVDD and VREFL is AVSS
6 VREFH is AVDD and VREFL is AVSS
7 VREFH is AVDD and VREFL is AVSS
OFFCAL
12
Input Offset Calibration Mode Select bit
0 Disable Offset Calibration mode; The inputs to the sample and hold amplifier are controlled by AD1CHS or AD1CSSL
1 Enable Offset Calibration mode; Positive and negative inputs of the sample and hold amplifier are connected to VREFL
CSCNA
10
Input Scan Select bit
0 Do not scan inputs
1 Scan inputs
BUFS
7
Buffer Fill Status bit
0 ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF
1 ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7
SMPI
5:2
Sample/Convert Sequences Per Interrupt Selection bits
0 Interrupts at the completion of conversion for each sample/convert sequence
1 Interrupts at the completion of conversion for each 2nd sample/convert sequence
2 Interrupts at the completion of conversion for each 3rd sample/convert sequence
3 Interrupts at the completion of conversion for each 4th sample/convert sequence
4 Interrupts at the completion of conversion for each 5th sample/convert sequence
5 Interrupts at the completion of conversion for each 6th sample/convert sequence
6 Interrupts at the completion of conversion for each 7th sample/convert sequence
7 Interrupts at the completion of conversion for each 8th sample/convert sequence
8 Interrupts at the completion of conversion for each 9th sample/convert sequence
9 Interrupts at the completion of conversion for each 10th sample/convert sequence
10 Interrupts at the completion of conversion for each 11th sample/convert sequence
11 Interrupts at the completion of conversion for each 12th sample/convert sequence
12 Interrupts at the completion of conversion for each 13th sample/convert sequence
13 Interrupts at the completion of conversion for each 14th sample/convert sequence
14 Interrupts at the completion of conversion for each 15th sample/convert sequence
15 Interrupts at the completion of conversion for each 16th sample/convert sequence
BUFM
1
ADC Result Buffer Mode Select bit
0 Buffer configured as one 16-word buffer ADC1BUFF-ADC1BUF0
1 Buffer configured as two 8-word buffers ADC1BUF7-ADC1BUF0 / ADC1BUFF-ADCBUF8
ALTS
0
Alternate Input Sample Mode Select bit
0 Always use Sample A input multiplexer settings
1 Uses Sample A input multiplexer settings for first sample then alternates between Sample B and Sample A input multiplexer settings for all subsequent samples
AD1CON3ADC Control Register 3
Address
0xBF809020
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
ADRC
15
ADC Conversion Clock Source bit
0 Clock derived from Peripheral Bus Clock (PBCLK)
1 Clock derived from FRC
SAMC
12:8
Auto-Sample Time bits
1 1 TAD
2 2 TAD
3 3 TAD
4 4 TAD
5 5 TAD
6 6 TAD
7 7 TAD
8 8 TAD
9 9 TAD
10 10 TAD
11 11 TAD
12 12 TAD
13 13 TAD
14 14 TAD
15 15 TAD
16 16 TAD
17 17 TAD
18 18 TAD
19 19 TAD
20 20 TAD
21 21 TAD
22 22 TAD
23 23 TAD
24 24 TAD
25 25 TAD
26 26 TAD
27 27 TAD
28 28 TAD
29 29 TAD
30 30 TAD
31 31 TAD
ADCS
7:0
ADC Conversion Clock Select bits
0 2*TPB
1 4*TPB
2 6*TPB
3 8*TPB
4 10*TPB
5 12*TPB
6 14*TPB
7 16*TPB
8 18*TPB
9 20*TPB
10 22*TPB
11 24*TPB
12 26*TPB
13 28*TPB
14 30*TPB
15 32*TPB
16 34*TPB
17 36*TPB
18 38*TPB
19 40*TPB
20 42*TPB
21 44*TPB
22 46*TPB
23 48*TPB
24 50*TPB
25 52*TPB
26 54*TPB
27 56*TPB
28 58*TPB
29 60*TPB
30 62*TPB
31 64*TPB
32 66*TPB
33 68*TPB
34 70*TPB
35 72*TPB
36 74*TPB
37 76*TPB
38 78*TPB
39 80*TPB
40 82*TPB
41 84*TPB
42 86*TPB
43 88*TPB
44 90*TPB
45 92*TPB
46 94*TPB
47 96*TPB
48 98*TPB
49 100*TPB
50 102*TPB
51 104*TPB
52 106*TPB
53 108*TPB
54 110*TPB
55 112*TPB
56 114*TPB
57 116*TPB
58 118*TPB
59 120*TPB
60 122*TPB
61 124*TPB
62 126*TPB
63 128*TPB
64 130*TPB
65 132*TPB
66 134*TPB
67 136*TPB
68 138*TPB
69 140*TPB
70 142*TPB
71 144*TPB
72 146*TPB
73 148*TPB
74 150*TPB
75 152*TPB
76 154*TPB
77 156*TPB
78 158*TPB
79 160*TPB
80 162*TPB
81 164*TPB
82 166*TPB
83 168*TPB
84 170*TPB
85 172*TPB
86 174*TPB
87 176*TPB
88 178*TPB
89 180*TPB
90 182*TPB
91 184*TPB
92 186*TPB
93 188*TPB
94 190*TPB
95 192*TPB
96 194*TPB
97 196*TPB
98 198*TPB
99 200*TPB
100 202*TPB
101 204*TPB
102 206*TPB
103 208*TPB
104 210*TPB
105 212*TPB
106 214*TPB
107 216*TPB
108 218*TPB
109 220*TPB
110 222*TPB
111 224*TPB
112 226*TPB
113 228*TPB
114 230*TPB
115 232*TPB
116 234*TPB
117 236*TPB
118 238*TPB
119 240*TPB
120 242*TPB
121 244*TPB
122 246*TPB
123 248*TPB
124 250*TPB
125 252*TPB
126 254*TPB
127 256*TPB
128 258*TPB
129 260*TPB
130 262*TPB
131 264*TPB
132 266*TPB
133 268*TPB
134 270*TPB
135 272*TPB
136 274*TPB
137 276*TPB
138 278*TPB
139 280*TPB
140 282*TPB
141 284*TPB
142 286*TPB
143 288*TPB
144 290*TPB
145 292*TPB
146 294*TPB
147 296*TPB
148 298*TPB
149 300*TPB
150 302*TPB
151 304*TPB
152 306*TPB
153 308*TPB
154 310*TPB
155 312*TPB
156 314*TPB
157 316*TPB
158 318*TPB
159 320*TPB
160 322*TPB
161 324*TPB
162 326*TPB
163 328*TPB
164 330*TPB
165 332*TPB
166 334*TPB
167 336*TPB
168 338*TPB
169 340*TPB
170 342*TPB
171 344*TPB
172 346*TPB
173 348*TPB
174 350*TPB
175 352*TPB
176 354*TPB
177 356*TPB
178 358*TPB
179 360*TPB
180 362*TPB
181 364*TPB
182 366*TPB
183 368*TPB
184 370*TPB
185 372*TPB
186 374*TPB
187 376*TPB
188 378*TPB
189 380*TPB
190 382*TPB
191 384*TPB
192 386*TPB
193 388*TPB
194 390*TPB
195 392*TPB
196 394*TPB
197 396*TPB
198 398*TPB
199 400*TPB
200 402*TPB
201 404*TPB
202 406*TPB
203 408*TPB
204 410*TPB
205 412*TPB
206 414*TPB
207 416*TPB
208 418*TPB
209 420*TPB
210 422*TPB
211 424*TPB
212 426*TPB
213 428*TPB
214 430*TPB
215 432*TPB
216 434*TPB
217 436*TPB
218 438*TPB
219 440*TPB
220 442*TPB
221 444*TPB
222 446*TPB
223 448*TPB
224 450*TPB
225 452*TPB
226 454*TPB
227 456*TPB
228 458*TPB
229 460*TPB
230 462*TPB
231 464*TPB
232 466*TPB
233 468*TPB
234 470*TPB
235 472*TPB
236 474*TPB
237 476*TPB
238 478*TPB
239 480*TPB
240 482*TPB
241 484*TPB
242 486*TPB
243 488*TPB
244 490*TPB
245 492*TPB
246 494*TPB
247 496*TPB
248 498*TPB
249 500*TPB
250 502*TPB
251 504*TPB
252 506*TPB
253 508*TPB
254 510*TPB
255 512*TPB
AD1CHSADC Input Select Register
Address
0xBF809040
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
CH0SB
27:24
Positive Input Select bits for Sample B
0 Channel 0 positive input is AN0
1 Channel 0 positive input is AN1
2 Channel 0 positive input is AN2
3 Channel 0 positive input is AN3
4 Channel 0 positive input is AN4
5 Channel 0 positive input is AN5
6 Channel 0 positive input is AN6
7 Channel 0 positive input is AN7
8 Channel 0 positive input is AN8
9 Channel 0 positive input is AN9
10 Channel 0 positive input is AN10
11 Channel 0 positive input is AN11
12 Channel 0 positive input is AN12
13 Channel 0 positive input is AN13
14 Channel 0 positive input is AN14
15 Channel 0 positive input is AN15
CH0NA
23
Negative Input Select bit for Sample A Multiplexer Setting
0 Channel 0 negative input is VREFL
1 Channel 0 negative input is AN1
CH0SA
19:16
Positive Input Select bits for Sample A Multiplexer Setting
BETA