PIC32MX775F512L ETH registers

The 39 registers of ETH (Ethernet controller), from 0xBF889000, with their reset value and every field. The PIC32MX775F512L has 789 registers in 67 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

ETH Ethernet controller

ETHCON1Ethernet Controller Control Register 1

Address
0xBF889000
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
ON15Ethernet ON bit
  • 0 Ethernet module is disabled
  • 1 Ethernet module is enabled
SIDL13Ethernet Stop in Idle Mode bit
  • 0 Ethernet module transfers continue during Idle mode
  • 1 Ethernet module transfers are paused during Idle mode
TXRTS9Transmit Request to Send bit
  • 0 Stop transmit (when cleared by software) or transmit done (when cleared by hardware)
  • 1 Activate the TX logic and send the packet(s) defined in the TX EDT
RXEN8Receive Enable bit
  • 0 Disable RX logic
  • 1 Enable RX logic
AUTOFC7Automatic Flow Control bit
  • 0 Automatic Flow Control disabled
  • 1 Automatic Flow Control enabled
MANFC4Manual Flow Control bit
  • 0 Manual Flow Control is disabled
  • 1 Manual Flow Control is enabled
BUFCDEC0
PTV31:16

ETHCON2Ethernet Controller Control Register 2

Address
0xBF889010
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXBUF_SZ10:4

ETHTXSTEthernet Controller TX Packet Descriptor Start Address Register

Address
0xBF889020
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXSTADDR2

ETHRXSTEthernet Controller RX Packet Descriptor Start Address Register

Address
0xBF889030
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXSTADDR2

ETHHT0Ethernet Controller Hash Table 0 Register

Address
0xBF889040
Reset
0x00000000
Access
read/write
Size
32-bit

ETHHT1Ethernet Controller Hash Table 1 Register

Address
0xBF889050
Reset
0x00000000
Access
read/write
Size
32-bit

ETHPMM0Ethernet Controller Pattern Match Mask 0 Register

Address
0xBF889060
Reset
0x00000000
Access
read/write
Size
32-bit

ETHPMM1Ethernet Controller Pattern Match Mask 1 Register

Address
0xBF889070
Reset
0x00000000
Access
read/write
Size
32-bit

ETHPMCSEthernet Controller Pattern Match Checksum Register

Address
0xBF889080
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PMCS15:0

ETHPMOEthernet Controller Pattern Match Offset Register

Address
0xBF889090
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PMO15:0

ETHRXFCEthernet Controller Receive Filter Configuration Register

Address
0xBF8890A0
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
HTEN15Enable Hash Table Filtering bit
  • 0 Disable Hash Table Filtering
  • 1 Enable Hash Table Filtering
MPEN14Magic Packet Enable bit
  • 0 Disable Magic Packet Filtering
  • 1 Enable Magic Packet Filtering
NOTPM12Pattern Match Inversion bit
  • 0 The Pattern Match Checksum must match for a successful Pattern Match to occur
  • 1 The Pattern Match Checksum must not match for a successful Pattern Match to occur
PMMODE11:8Pattern Match Mode bits
  • 0 Pattern Match is disabled; pattern match is always unsuccessful
  • 1 Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches)
  • 2 Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND(Destination Address = Station Address)
  • 3 Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND (Destination Address = Station Address)
  • 4 Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND (Destination Address = Unicast Address)
  • 5 Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND (Destination Address = Unicast Address)
  • 6 Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND (Destination Address = Broadcast Address)
  • 7 Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND(Destination Address = Broadcast Address)
  • 8 Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND (Hash Table Filter match)(1
  • 9 Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND (Packet = Magic Packet)(1
CRCERREN7CRC Error Collection Enable bit
  • 0 Disable CRC Error Collection filtering
  • 1 The received packet CRC must be invalid for the packet to be accepted
CRCOKEN6CRC OK Enable bit
  • 0 Disable CRC filtering
  • 1 The received packet CRC must be valid for the packet to be accepted
RUNTERREN5Runt Error Collection Enable bit
  • 0 Disable Runt Error Collection filtering
  • 1 The received packet must be a runt packet for the packet to be accepted
RUNTEN4Runt Enable bit
  • 0 Disable Runt filtering
  • 1 The received packet must not be a runt packet for the packet to be accepted
UCEN3Unicast Enable bit
  • 0 Disable Unicast Filtering
  • 1 Enable Unicast Filtering
NOTMEEN2Not Me Unicast Enable bit
  • 0 Disable Not Me Unicast Filtering
  • 1 Enable Not Me Unicast Filtering
MCEN1Multicast Enable bit
  • 0 Disable Multicast Filtering
  • 1 Enable Multicast Filtering
BCEN0Broadcast Enable bit
  • 0 Disable Broadcast Filtering
  • 1 Enable Broadcast Filtering

ETHRXWMEthernet Controller Receive Watermarks Register

Address
0xBF8890B0
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
RXFWM23:16
RXEWM7:0

ETHIENEthernet Controller Interrupt Enable Register

Address
0xBF8890C0
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
TXBUSEIE14Transmit BVCI Bus Error Interrupt Enable bit
  • 0 Disable TXBUS Error Interrupt
  • 1 Enable TXBUS Error Interrupt
RXBUSEIE13Receive BVCI Bus Error Interrupt Enable bit
  • 0 Disable RXBUS Error Interrupt
  • 1 Enable RXBUS Error Interrupt
EWMARKIE9Empty Watermark Interrupt Enable bit
  • 0 Disable EWMARK Interrupt
  • 1 Enable EWMARK Interrupt
FWMARKIE8Full Watermark Interrupt Enable bit
  • 0 Disable FWMARK Interrupt
  • 1 Enable FWMARK Interrupt
RXDONEIE7Receiver Done Interrupt Enable bit
  • 0 Disable RXDONE Interrupt
  • 1 Enable RXDONE Interrupt
PKTPENDIE6Packet Pending Interrupt Enable bit
  • 0 Disable PKTPEND Interrupt
  • 1 Enable PKTPEND Interrupt
RXACTIE5RX Activity Interrupt Enable bit
  • 0 Disable RXACT Interrupt
  • 1 Enable RXACT Interrupt
TXDONEIE3Transmitter Done Interrupt Enable bit
  • 0 Disable TXDONE Interrupt
  • 1 Enable TXDONE Interrupt
TXABORTIE2Transmitter Abort Interrupt Enable bit
  • 0 Disable TXABORT Interrupt
  • 1 Enable TXABORT Interrupt
RXBUFNAIE1Receive Buffer Not Available Interrupt Enable bit
  • 0 Disable RXBUFNA Interrupt
  • 1 Enable RXBUFNA Interrupt
RXOVFLWIE0Receive FIFO Overflow Interrupt Enable bit
  • 0 Disable RXOVFLW Interrupt
  • 1 Enable RXOVFLW Interrupt

ETHIRQEthernet Controller Interrupt Request Register

Address
0xBF8890D0
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
TXBUSE14Transmit BVCI Bus Error Interrupt bit
  • 0 BVCI Bus Error has not occurred
  • 1 BVCI Bus Error has occurred
RXBUSE13Receive BVCI Bus Error Interrupt bit
  • 0 BVCI Bus Error has not occurred
  • 1 BVCI Bus Error has occurred
EWMARK9Empty Watermark Interrupt bit
  • 0 No interrupt pending
  • 1 Empty Watermark pointer reached
FWMARK8Full Watermark Interrupt bit
  • 0 No interrupt pending
  • 1 Full Watermark pointer reached
RXDONE7Receive Done Interrupt bit
  • 0 No interrupt pending
  • 1 RX packet was successfully received
PKTPEND6Packet Pending Interrupt bit
  • 0 RX packet is not pending in memory
  • 1 RX packet pending in memory
RXACT5Receive Activity Interrupt bit
  • 0 No interrupt pending
  • 1 RX packet data was successfully received
TXDONE3Transmit Done Interrupt bit
  • 0 No interrupt pending
  • 1 TX packet was successfully sent
TXABORT2Transmit Abort Condition Interrupt bit
  • 0 No interrupt pending
  • 1 TX abort condition occurred on the last TX packet
RXBUFNA1Receive Buffer Not Available Interrupt bit
  • 0 No interrupt pending
  • 1 RX Buffer Descriptor Not Available condition has occurred
RXOVFLW0Receive FIFO Over Flow Error bit
  • 0 No interrupt pending
  • 1 RX FIFO Overflow Error condition has occurred

ETHSTATEthernet Controller Status Register

Address
0xBF8890E0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
BUFCNT23:16
BUSY7
TXBUSY6Transmit Busy bit
  • 0 TX logic is idle
  • 1 TX logic is receiving data
RXBUSY5Receive Busy bit
  • 0 RX logic is idle
  • 1 RX logic is receiving data

RXOVFLOW

Address
0xBF889100
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXOVFLWCNT15:0

ETHFRMTXOKEthernet Controller Frames Transmitted OK Statistics Register

Address
0xBF889110
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FRMTXOKCNT0

ETHSCOLFRMEthernet Controller Single Collision Frames Statistics Register

Address
0xBF889120
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SCOLFRMCNT15:0

ETHMCOLFRMEthernet Controller Multiple Collision Frames Statistics Register

Address
0xBF889130
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
MCOLFRMCNT15:0

ETHFRMRXOKEthernet Controller Frames Received OK Statistics Register

Address
0xBF889140
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FRMRXOKCNT15:0

ETHFCSERREthernet Controller Frame Check Sequence Error Statistics Register

Address
0xBF889150
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FCSERRCNT15:0

ETHALGNERREthernet Controller Alignment Errors Statistics Register

Address
0xBF889160
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ALGNERRCNT15:0

EMAC1CFG1Ethernet Controller MAC Configuration 1 Register

Address
0xBF889200
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
SOFTRESET15
SIMRESET14
RESETRMCS11
RESETRFUN10
RESETTMCS9
RESETTFUN8
LOOPBACK4MAC Loopback mode bit
  • 0 MAC normal operation
  • 1 MAC Transmit interface is loop backed to the MAC Receive interface
TXPAUSE3MAC TX Flow Control bit
  • 0 PAUSE Flow Control frames are blocked
  • 1 PAUSE Flow Control frames are allowed to be transmitted
RXPAUSE2MAC RX Flow Control bit
  • 0 Received PAUSE Flow Control frames are ignored
  • 1 The MAC acts upon received PAUSE Flow Control frames
PASSALL1MAC Pass all Receive Frames bit
  • 0 The received Control frames are ignored
  • 1 The MAC will accept all frames regardless of type (Normal vs. Control)
RXENABLE0MAC Receive Enable bit
  • 0 Disable the MAC receiving of frames
  • 1 Enable the MAC receiving of frames

EMAC1CFG2Ethernet Controller MAC Configuration 2 Register

Address
0xBF889210
Reset
0x00000000
Access
read/write
Size
32-bit
13 fields
FieldBitsWhat it does
EXCESSDFR14
BPNOBKOFF13Backpressure/No Backoff bit
  • 0 The MAC will not remove the backoff
  • 1 The MAC after incidentally causing a collision during backpressure will immediately retransmit without backoff reducing the chance of further collisions and ensuring transmit packets get sent
NOBKOFF12No Backoff bit
  • 0 Following a collision
  • 1 Following a collision
LONGPRE9Long Preamble Enforcement bit
  • 0 The MAC allows any length preamble as per the Standard
  • 1 The MAC only allows receive packets which contain preamble fields less than 12 bytes in length
PUREPRE8Pure Preamble Enforcement bit
  • 0 The MAC does not perform any preamble checking
  • 1 The MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with errors in its preamble is discarded
AUTOPAD7Automatic Detect Pad Enable bit
  • 0 The MAC does not perform automatic detection
  • 1 The MAC will automatically detect the type of frame
VLANPAD6VLAN Pad Enable bit
  • 0 The MAC does not perform padding of short frames
  • 1 The MAC will pad all short frames to 64 bytes and append a valid CRC
PADENABLE5Pad/CRC Enable bit
  • 0 The frames presented to the MAC have a valid length
  • 1 The MAC will pad all short frames
CRCENABLE4CRC Enable1 bit
  • 0 The frames presented to the MAC have a valid CRC
  • 1 The MAC will append a CRC to every frame whether padding was required or not. Must be set if the PADENABLE bit is set.
DELAYCRC3Delayed CRC bit
  • 0 No proprietary header
  • 1 Four bytes of header (ignored by the CRC function)
HUGEFRM2Huge Frame enable bit
  • 0 Huge frames are not allowed for receive or transmit
  • 1 Frames of any length are transmitted and received
LENGTHCK1Frame Length checking bit
  • 0 Length/Type field check is not performed
  • 1 Both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported on the transmit/receive statistics vector.
FULLDPLX0Full-Duplex Operation bit
  • 0 The MAC operates in Half-Duplex mode
  • 1 The MAC operates in Full-Duplex mode

EMAC1IPGTEthernet Controller MAC Back-to-Back Interpacket Gap Register

Address
0xBF889220
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
B2BIPKTGP6:0

EMAC1IPGREthernet Controller MAC Non-Back-to-Back Interpacket Gap Register

Address
0xBF889230
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
NB2BIPKTGP114:8
NB2BIPKTGP26:0

EMAC1CLRTEthernet Controller MAC Collision Window/Retry Limit Register

Address
0xBF889240
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
CWINDOW8
RETX3:0

EMAC1MAXFEthernet Controller MAC Maximum Frame Length Register

Address
0xBF889250
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
MACMAXF0

EMAC1SUPPEthernet Controller MAC PHY Support Register

Address
0xBF889260
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
RESETRMII11Reset RMII Logic bit
  • 0 Normal operation.
  • 1 Reset the MAC RMII module
SPEEDRMII8RMII Speed bit
  • 0 RMII is running at 10 Mbps
  • 1 RMII is running at 100 Mbps

EMAC1TESTEthernet Controller MAC Test Register

Address
0xBF889270
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
TESTBP2Test Backpressure bit
  • 0 Normal operation
  • 1 The MAC will assert backpressure on the link. Backpressure causes preamble to be transmitted
TESTPAUSE1Test PAUSE bit
  • 0 Normal operation
  • 1 The MAC Control sub-layer will inhibit transmissions
SHRTQNTA0Shortcut PAUSE Quanta bit
  • 0 Normal operation
  • 1 The MAC reduces the effective PAUSE Quanta from 64 byte-times to 1 byte-time

EMAC1MCFGEthernet Controller MAC MII Management Configuration Register

Address
0xBF889280
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
RESETMGMT15Test Reset MII Management bit
  • 0 Normal Operation
  • 1 Reset the MII Management module
CLKSEL2
NOPRE1Suppress Preamble bit
  • 0 Normal read/write cycles are performed
  • 1 The MII Management will perform read/write cycles without the 32-bit preamble field. Some PHYs support suppressed preamble
SCANINC0Scan Increment bit
  • 0 Continuous reads of the same PHY
  • 1 The MII Management module will perform read cycles across a range of PHYs. The read cycles will start from address 1 through the value set in EMAC1MADR

EMAC1MCMDEthernet Controller MAC MII Management Command Register

Address
0xBF889290
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
SCAN1MII Management Scan Mode bit
  • 0 Normal Operation
  • 1 The MII Management module will perform read cycles continuously (for example
READ0MII Management Read Command bit
  • 0 The MII Management module will perform a write cycle. The write data is taken from the EMAC1MWTD register
  • 1 The MII Management module will perform a single read cycle. The read data is returned in the EMAC1MRDD register

EMAC1MADREthernet Controller MAC MII Management Address Register

Address
0xBF8892A0
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
PHYADDR8
REGADDR0

EMAC1MWTDEthernet Controller MAC MII Management Write Data Register

Address
0xBF8892B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PEMACMWTD15:0

EMAC1MRDDEthernet Controller MAC MII Management Read Data Register

Address
0xBF8892C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
MRDD0

EMAC1MINDEthernet Controller MAC MII Management Indicators Register

Address
0xBF8892D0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
LINKFAIL3
NOTVALID2
SCAN1
MIIMBUSY0

EMAC1SA0Ethernet Controller MAC Station Address 0 Register

Address
0xBF889300
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
STNADDR68
STNADDR50

EMAC1SA1Ethernet Controller MAC Station Address 1 Register

Address
0xBF889310
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
STNADDR48
STNADDR30

EMAC1SA2Ethernet Controller MAC Station Address 2 Register

Address
0xBF889320
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
STNADDR28
STNADDR10