PIC32MX775F512L SPI3 registers

The 4 registers of SPI3 (SPI 3), from 0xBF805800, with their reset value and every field. The PIC32MX775F512L has 789 registers in 67 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

SPI3 SPI 3

SPI3CONSPI Control Register

Address
0xBF805800
Reset
0x00000000
Access
read/write
Size
32-bit
20 fields
FieldBitsWhat it does
FRMSYNC30Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only)
  • 0 Frame sync pulse output (Master mode)
  • 1 Frame sync pulse input (Slave mode)
FRMPOL29Frame Sync Polarity bit (Framed SPI mode only)
  • 0 Frame pulse is active-low
  • 1 Frame pulse is active-high
MSSEN28Master Mode Slave Select Enable bit
  • 0 Slave select SPI support is disabled.
  • 1 Slave select SPI support enabled. The SS pin is automatically driven during transmission in Master mode. Polarity is determined by the FRMPOL bit.
FRMSYPW27Frame Sync Pulse Width bit
  • 0 Frame sync pulse is one clock wide
  • 1 Frame sync pulse is one character wide
FRMCNT26:24Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per pulse. This bit is only valid in FRAMED_SYNC mode.
  • 0 Generate a frame sync pulse on every data character
  • 1 Generate a frame sync pulse on every 2 data characters
  • 2 Generate a frame sync pulse on every 4 data characters
  • 3 Generate a frame sync pulse on every 8 data characters
  • 4 Generate a frame sync pulse on every 16 data characters
  • 5 Generate a frame sync pulse on every 32 data characters
  • 6 Reserved
  • 7 Reserved
SPIFE17Frame Sync Pulse Edge Select bit
  • 0 Frame synchronization pulse precedes the first bit clock
  • 1 Frame synchronization pulse coincides with the first bit clock
ENHBUF16Enhanced Buffer Enable bit
  • 0 Enhanced Buffer mode is disabled
  • 1 Enhanced Buffer mode is enabled
ON15SPI Peripheral On bit
  • 0 SPI Peripheral is disabled
  • 1 SPI Peripheral is enabled
SIDL13Stop in Idle Mode bit
  • 0 Continue operation in Idle mode
  • 1 Discontinue operation when CPU enters in Idle mode
DISSDO12Disable SDOx pin bit
  • 0 SDOx pin is controlled by the module
  • 1 SDOx pin is not used by the module. Pin is controlled by associated PORT register
MODE321132/16-Bit Communication Select bits
  • 0 (AUDEN=1) 16-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame / (AUDEN=0) 8-bit communication
  • 1 (AUDEN=1) 16-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame / (AUDEN=0) 16-bit communication
  • 2 (AUDEN=1) 32-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame / (AUDEN=0) 32-bit communication
  • 3 (AUDEN=1) 24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame / (AUDEN=0) 32-bit communication
MODE1610
SMP9SPI Data Input Sample Phase bit (master mode only)
  • 0 (Master mode) Input data sampled at middle of data output time / (Slave mode) value is ignored
  • 1 (Master mode) Input data sampled at end of data output time / (Slave mode) value is ignored
CKE8SPI Clock Edge Select bit
  • 0 Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)
  • 1 Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)
SSEN7Slave Select Enable bit
  • 0 SSx pin not used for Slave mode
  • 1 SSx pin used for Slave mode
CKP6Clock Polarity Select bit
  • 0 Idle state for clock is a low level; active state is a high level
  • 1 Idle state for clock is a high level; active state is a low level
MSTEN5Master Mode Enable bit
  • 0 Slave mode
  • 1 Master mode
STXISEL3:2SPI Transmit Buffer Empty Interrupt Mode bits
  • 0 Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are complete
  • 1 Interrupt is generated when the buffer is completely empty
  • 2 Interrupt is generated when the buffer is empty by one-half or more
  • 3 Interrupt is generated when the buffer is not full (has one or more empty elements)
SRXISEL1:0SPI Receive Buffer Full Interrupt Mode bits
  • 0 Interrupt is generated when the last word in the receive buffer is read (i.e. buffer is empty)
  • 1 Interrupt is generated when the buffer is not empty
  • 2 Interrupt is generated when the buffer is full by one-half or more
  • 3 Interrupt is generated when the buffer is full
FRMEN31Framed SPI Support bit
  • 0 Framed SPI support is disabled
  • 1 Framed SPI support is enabled (SSx pin used as FSYNC input/output)

SPI3STAT

Address
0xBF805810
Reset
0x00000000
Access
read only
Size
32-bit
10 fields
FieldBitsWhat it does
RXBUFELM28:24
TXBUFELM20:16
SPIBUSY11SPI Activity Status bit
  • 0 SPI peripheral is currently idle
  • 1 SPI peripheral is currently busy with some transactions
SPITUR8Transmit Under Run bit
  • 0 Transmit buffer has no underrun condition
  • 1 Transmit buffer has encountered an underrun condition
SRMT7Shift Register Empty bit (valid only when ENHBUF = 1)
  • 0 When SPI module shift register is not empty
  • 1 When SPI module shift register is empty
SPIROV6Receive Overflow Flag bit
  • 0 No overflow has occurred
  • 1 A new data is completely received and discarded. The user software has not read the previous data in the SPIxBUF register.
SPIRBE5RX FIFO Empty bit (valid only when ENHBUF = 1)
  • 0 RX FIFO is not empty (CRPTR != SWPTR)
  • 1 RX FIFO is empty (CRPTR = SWPTR)
SPITBE3SPI Transmit Buffer Empty Status bit
  • 0 Transmit buffer SPIxTXB is not empty
  • 1 Transmit buffer SPIxTXB is empty
SPITBF1SPI Transmit Buffer Full Status bit
  • 0 Transmit buffer is not full
  • 1 Transmit not yet started SPITXB is full
SPIRBF0SPI Receive Buffer Full Status bit
  • 0 Receive buffer SPIxRXB is not full
  • 1 Receive buffer SPIxRXB is full

SPI3BUF

Address
0xBF805820
Reset
0x00000000
Access
read/write
Size
32-bit

SPI3BRG

Address
0xBF805830
Reset
0x00000000
Access
read/write
Size
32-bit