PIC32MX795F512L PMP registers

The 7 registers of PMP (Parallel master port), from 0xBF807000, with their reset value and every field. The PIC32MX795F512L has 789 registers in 67 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

PMP Parallel master port

PMCONParallel Port Control Register

Address: 0xBF807000
Reset: 0x00000000
Access: read/write
Size: 32-bit

12 fields

Field	Bits	What it does
ON	15	Parallel Master Port Enable bit `0` PMP is disabled, no off-chip access performed `1` PMP is enabled
SIDL	13	Stop in Idle Mode bit `0` Continue module operation in Idle mode `1` Discontinue module operation when device enters Idle mode
ADRMUX	12:11	Address/Data Multiplexing Selection bits `0` Address and data appear on separate pins `1` Lower 8 bits of address are multiplexed on PMD(7:0) pins, upper bits are on PMA(15:8) `2` All 16 bits of address are multiplexed on PMD(7:0) pins `3` All 16 bits of address are multiplexed on PMD(15:0) pins
PMPTTL	10	PMP Module TTL Input Buffer Select bit `0` PMP module uses Schmitt Trigger input buffer `1` PMP module uses TTL input buffers
PTWREN	9	Write Enable Strobe Port Enable bit `0` PMWR/PMENB port is disabled `1` PMWR/PMENB port is enabled
PTRDEN	8	Read/Write Strobe Port Enable bit `0` PMRD/PMWR port is disabled `1` PMRD/PMWR port is enabled
CSF	7:6	Chip Select Function bits `0` PMCS2 and PMCS1 function as address bits 15 and 14 `1` PMCS2 functions as Chip Select, PMCS1 functions as address bit 14 `2` PMCS2 and PMCS1 function as Chip Select `3` Reserved
ALP	5	Address Latch Polarity bit `0` Active-low (PMALL and PMALH) `1` Active-high (PMALL and PMALH)
CS2P	4	Chip Select 2 Polarity bit `0` Active-low (PMCS2) `1` Active-high (PMCS2)
CS1P	3	Chip Select 1 Polarity bit `0` Active-low (PMCS1) `1` Active-high (PMCS1)
WRSP	1	Write Strobe Polarity bit `0` (Slave and Master mode 2) Write strobe active-low / (Master mode 1) Enable strobe active-low `1` (Slave and Master mode 2) Write strobe active-high / (Master mode 1) Enable strobe active-high
RDSP	0	Read Strobe Polarity bit `0` (Slave and Master mode 2) Read Strobe active-low / (Master mode 1) Read/write strobe active-low `1` (Slave and Master mode 2) Read Strobe active-high / (Master mode 1) Read/write strobe active-high

PMMODEParallel Port Mode Register

Address: 0xBF807010
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
BUSY	15	Busy bit (Master mode only) `0` Port is not busy `1` Port is busy
IRQM	14:13	Interrupt Request Mode bits `0` No Interrupt generated `1` Interrupt generated at the end of the read/write cycle `2` Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA(1:0) =11 (Addressable Slave mode only) `3` Reserved
INCM	12:11	Increment Mode bits `0` No increment or decrement of address `1` Increment ADDR(15:0) by 1 every read/write cycle `2` Decrement ADDR(15:0) by 1 every read/write cycle `3` Slave mode read and write buffers auto-increment (MODE(1:0) = 00 only)
MODE16	10
MODE	9:8	Parallel Port Mode Select bits `0` Legacy Parallel Slave Port (PMRD, PMWR, PMCS1, and PMD) `1` Enhanced Slave mode (PMRD, PMWR, PMCS1, PMD, and PMA) `2` Master mode 2 (PMCS1, PMRD, PMWR, PMA, and PMD) `3` Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMA, and PMD)
WAITB	7:6	Data Setup to Read/Write Strobe Wait States bits `0` Data wait of 1 TPB; multiplexed address phase of 1 TPB (default) `1` Data wait of 2 TPB; multiplexed address phase of 2 TPB `2` Data wait of 3 TPB; multiplexed address phase of 3 TPB `3` Data wait of 4 TPB; multiplexed address phase of 4 TPB
WAITM	5:2	Data Read/Write Strobe Wait States bits `0` Wait of 1TPB (default) `1` Wait of 2TPB `2` Wait of 3TPB `3` Wait of 4TPB `4` Wait of 5TPB `5` Wait of 6TPB `6` Wait of 7TPB `7` Wait of 8TPB `8` Wait of 9TPB `9` Wait of 10TPB `10` Wait of 11TPB `11` Wait of 12TPB `12` Wait of 13TPB `13` Wait of 14TPB `14` Wait of 15TPB `15` Wait of 16TPB
WAITE	1:0	Data Hold After Read/Write Strobe Wait States bits `0` (for write operations) Wait of 1 TPB (default) / (for read operations) Wait of 0 TPB (default) `1` (for write operations) Wait of 2 TPB / (for read operations) Wait of 1 TPB `2` (for write operations) Wait of 3 TPB / (for read operations) Wait of 2 TPB `3` (for write operations) Wait of 4 TPB / (for read operations) Wait of 3 TPB

PMADDRParallel Port Address Register

Address: 0xBF807020
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
CS	14	Chip Select bit `0` Chip Select 1 and 2 are inactive `1` Chip Select 1 is active, Chip Select 2 is inactive `2` Chip Select 1 is inactive, Chip Select 2 is active `3` Chip Select 1 and 2 are active
ADDR	13:0

PMDOUTParallel Port Output Data Register

Address: 0xBF807030
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATAOUT	31:0	Port Data Output bits `0` Data output is 0

PMDINParallel Port Input Data Register

Address: 0xBF807040
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATAIN	31:0	Port Data Input bits `0` Data input is 0

PMAENParallel Port Pin Enable Register

Address: 0xBF807050
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
PTEN	15:0	PMALH/PMALL Strobe Enable bits `0` PMA14 functions as port I/O `0` PMA(10:2) function as port I/O `0` PMA1 and PMA0 pads function as port I/O `1` PMA1 and PMA0 function as either PMA(1:0) or PMALH and PMALL `4` PMA(10:2) function as PMP address lines `16384` PMA14 functions as either PMA(14) or PMCS1

PMSTATParallel Port Status Register (Slave modes only)

Address: 0xBF807060
Reset: 0x0000008F
Access: read/write
Size: 32-bit

12 fields

Field	Bits	What it does
IBF	15	Input Buffer Full Status bit `0` Some or all of the writable input buffer registers are empty `1` All writable input buffer registers are full
IBOV	14	Input Buffer Overflow Status bit `0` No overflow occurred `1` A write attempt to a full input byte buffer occurred (must be cleared in software)
IB3F	11	Input Buffer 3 Status Full bit `0` Input Buffer does not contain any unread data `1` Input Buffer contains data that has not been read (reading buffer will clear this bit)
IB2F	10	Input Buffer 2 Status Full bit `0` Input Buffer does not contain any unread data `1` Input Buffer contains data that has not been read (reading buffer will clear this bit)
IB1F	9	Input Buffer 1 Status Full bit `0` Input Buffer does not contain any unread data `1` Input Buffer contains data that has not been read (reading buffer will clear this bit)
IB0F	8	Input Buffer 0 Status Full bit `0` Input Buffer does not contain any unread data `1` Input Buffer contains data that has not been read (reading buffer will clear this bit)
OBE	7	Output Buffer Empty Status bit `0` Some or all of the readable output buffer registers are full `1` All readable output buffer registers are empty
OBUF	6	Output Buffer Underflow Status bit `0` No underflow occurred `1` A read occurred from an empty output byte buffer (must be cleared in software)
OB3E	3	Output Buffer 3 Status Empty bit `0` Output buffer contains data that has not been transmitted `1` Output buffer is empty (writing data to the buffer will clear this bit)
OB2E	2	Output Buffer 2 Status Empty bit `0` Output buffer contains data that has not been transmitted `1` Output buffer is empty (writing data to the buffer will clear this bit)
OB1E	1	Output Buffer 1 Status Empty bit `0` Output buffer contains data that has not been transmitted `1` Output buffer is empty (writing data to the buffer will clear this bit)
OB0E	0	Output Buffer 0 Status Empty bit `0` Output buffer contains data that has not been transmitted `1` Output buffer is empty (writing data to the buffer will clear this bit)