The 6 registers of RTCC (Real-time clock and calendar), from 0xBF800200, with their reset value and every field. The PIC32MX795F512L has 789 registers in 67 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
RTCC Real-time clock and calendar
RTCCONRTC Control Register
Address
0xBF800200
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
CAL
25:16
RTC Drift Calibration bits
0 No adjustment
1 Minimum positive adjustment, adds 1 RTC clock pulse every one minute
511 Maximum positive adjustment, adds 511 RTC clock pulses every one minute
512 Maximum negative adjustment, subtracts 512 clock pulses every one minute
1023 Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute
ON
15
RTCC On bit
0 RTCC module is disabled
1 RTCC module is enabled
SIDL
13
Stop in Idle Mode bit
0 Continue normal operation in Idle mode
1 Disables the PBCLK to the RTCC when CPU enters in Idle mode
RTSECSEL
7
RTCC Seconds Clock Output Select bit
0 RTCC Alarm Pulse is selected for the RTCC pin
1 RTCC Seconds Clock is selected for the RTCC pin
RTCCLKON
6
RTCC Clock Enable Status bit
0 RTCC Clock is not running
1 RTCC Clock is actively running
RTCWREN
3
RTC Value Registers Write Enable bit
0 RTC Value registers are locked out from being written to by the user
1 RTC Value registers can be written to by the user
RTCSYNC
2
RTCC Value Registers Read Synchronization bit
0 RTC Value registers can be read without concern about a rollover ripple
1 RTC Value registers can change while reading due to a rollover ripple that results in an invalid data read
HALFSEC
1
Half-Second Status bit
0 First half period of a second
1 Second half period of a second
RTCOE
0
RTCC Output Enable bit
0 RTCC clock output is disabled
1 RTCC clock output is enabled clock presented onto an I/O
RTCALRMRTC ALARM Control Register
Address
0xBF800210
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
ALRMEN
15
Alarm Enable bit
0 Alarm is disabled
1 Alarm is enabled
CHIME
14
Chime Enable bit
0 Chime is disabled ARPT(7:0) stops once it reaches 0x00
1 Chime is enabled ARPT(7:0) is allowed to rollover from 0x00 to 0xFF
PIV
13
Alarm Pulse Initial Value bit
0 (When ALRMEN = 0) Alarm pulse low / (When ALRMEN = 1) PIV is read-only and returns state of the alarm pulse.
1 (When ALRMEN = 0) Alarm pulse high / (When ALRMEN = 1) PIV is read-only and returns state of the alarm pulse.
ALRMSYNC
12
Alarm Sync bit
0 ARPT(7:0) and ALRMEN can be read without concerns of rollover because the prescaler is more than 32 RTC clocks away from a half-second rollover
1 ARPT(7:0) and ALRMEN may change as a result of a half second rollover during a read.
AMASK
11:8
Alarm Mask Configuration bits
0 Every half-second
1 Every second
2 Every 10 seconds
3 Every minute
4 Every 10 minutes
5 Every hour
6 Once a day
7 Once a week
8 Once a month
9 Once a year (except when configured for February 29
BETA