The 14 registers of PORTG (I/O port G), from 0xBF860600, with their reset value and every field. The PIC32MZ0512EFK064 has 1518 registers in 86 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
PORTG I/O port G
ANSELG
Address
0xBF860600
Reset
0x000003C0
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
ANSG9
9
ANSG8
8
ANSG7
7
ANSG6
6
TRISG
Address
0xBF860610
Reset
0x000003C0
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
TRISG9
9
TRISG8
8
TRISG7
7
TRISG6
6
PORTG
Address
0xBF860620
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
RG9
9
RG8
8
RG7
7
RG6
6
LATG
Address
0xBF860630
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
LATG9
9
LATG8
8
LATG7
7
LATG6
6
ODCG
Address
0xBF860640
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
ODCG9
9
ODCG8
8
ODCG7
7
ODCG6
6
CNPUG
Address
0xBF860650
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
CNPUG9
9
CNPUG8
8
CNPUG7
7
CNPUG6
6
CNPDG
Address
0xBF860660
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
CNPDG9
9
CNPDG8
8
CNPDG7
7
CNPDG6
6
CNCONGChange Notice control for PORTx Register
Address
0xBF860670
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
ON
15
Change Notice Control ON bit
0 CN is disabled
1 CN is enabled
EDGEDETECT
11
Change Notification Style bit
0 Mismatch Style. Detect change from last PORTx read (CNSTATx used for CN Event).
1 Edge Style. Detect edge transitions (CNFx used for CN Event).
BETA