PIC32MZ1024EFE064 ADC registers

The 83 registers of ADC (Analog-to-digital converter), from 0xBF84B000, with their reset value and every field. The PIC32MZ1024EFE064 has 1143 registers in 83 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

ADC Analog-to-digital converter

ADCCON1ADC Control Register 1

Address
0xBF84B000
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
TRBERR30Turbo Channel Error Status bit
  • 0 Turbo channel error did not occur
  • 1 An error occurred while setting the Turbo channel and Turbo channel function to be disabled regardless of the TRBEN bit being set to 1.
TRBMST29:27Turbo Master ADCx bits
  • 0 ADC0 is selected as the Turbo Master
  • 1 ADC1 is selected as the Turbo Master
  • 2 ADC2 is selected as the Turbo Master
  • 3 ADC3 is selected as the Turbo Master
  • 4 ADC4 is selected as the Turbo Master
  • 5 Reserved
  • 6 Reserved
  • 7 Reserved
TRBSLV26:24Turbo Slave ADCx bits
  • 0 ADC0 is selected as the Turbo Slave
  • 1 ADC1 is selected as the Turbo Slave
  • 2 ADC2 is selected as the Turbo Slave
  • 3 ADC3 is selected as the Turbo Slave
  • 4 ADC4 is selected as the Turbo Slave
  • 5 Reserved
  • 6 Reserved
  • 7 Reserved
FRACT23Fractional Data Output Format bit
  • 0 Integer
  • 1 Fractional
SELRES22:21Shared ADC Resolution bits
  • 0 6 bits
  • 1 8 bits
  • 2 10 bits
  • 3 12 bits (default)
STRGSRC20:16Scan Trigger Source Select bits
  • 0 No Trigger
  • 1 Global software edge trigger (GSWTRG)
  • 2 Global level software trigger (GLSWTRG)
  • 3 Reserved
  • 4 INT0 External interrupt
  • 5 TMR1 match
  • 6 TMR3 match
  • 7 TMR5 match
  • 8 OCMP1
  • 9 OCMP3
  • 10 OCMP5
  • 11 Comparator 1 (COUT)
  • 12 Comparator 2 (COUT)
  • 13 Reserved
  • 31 Reserved
ON15ADC Module Enable bit
  • 0 ADC module is disabled
  • 1 ADC module is enabled
SIDL13Stop in Idle Mode bit
  • 0 Continue module operation in Idle mode
  • 1 Discontinue module operation when device enters Idle mode
AICPMPEN12Analog Input Charge Pump Enable bit - see datasheet
  • 0 Analog input charge pump is disabled
  • 1 Analog input charge pump is enabled (default)
CVDEN11Capacitive Voltage Division Enable bit
  • 0 CVD operation is disabled
  • 1 CVD operation is enabled
FSSCLKEN10Fast Synchronous System Clock to ADC Control Clock bit
  • 0 Fast synchronous system clock to ADC control clock is disabled
  • 1 Fast synchronous system clock to ADC control clock is enabled
FSPBCLKEN9Fast Synchronous Peripheral Clock to ADC Control Clock bit
  • 0 Fast synchronous peripheral clock to ADC control clock is disabled
  • 1 Fast synchronous peripheral clock to ADC control clock is enabled
IRQVS6:4Interrupt Vector Shift bits
  • 0 Shift x left 0 bit position
  • 1 Shift x left 1 bit position
  • 2 Shift x left 2 bit position
  • 3 Shift x left 3 bit position
  • 4 Shift x left 4 bit position
  • 5 Shift x left 5 bit position
  • 6 Shift x left 6 bit position
  • 7 Shift x left 7 bit position
STRGLVL3Scan Trigger High Level/Positive Edge Sensitivity bit
  • 0 Scan trigger is positive edge sensitive. Once STRIG mode is selected (TRGSRCx in the ADCTRGx register)
  • 1 Scan trigger is high level sensitive. Once STRIG mode is selected (TRGSRCx in the ADCTRGx register)
TRBEN31Turbo Channel Enable bit
  • 0 Disable the Turbo channel
  • 1 Enable the Turbo channel

ADCCON2ADC Control Register 2

Address
0xBF84B004
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
REFFLT30Band Gap/ Vref / AVdd BOR Fault Status bit
  • 0 Band gap and Vref voltage are working properly
  • 1 Fault in band gap or the Vref voltage while the ON bit (ADCCON1) was set. Most likely a band gap orVref fault will be caused by a BOR of the analog Vdd supply.
EOSRDY29End of Scan Interrupt Status bit
  • 0 Scanning has not completed
  • 1 All analog inputs are considered for scanning through the scan trigger (all analog inputs specified in the ADCCSS1 and ADCCSS2 registers) have completed scanning
CVDCPL28:26Capacitor Voltage Divider Setting bit
  • 0 0 * 2.5 pF = 0 pF
  • 1 1 * 2.5 pF = 2.5 pF
  • 2 2 * 2.5 pF = 5 pF
  • 3 3 * 2.5 pF = 7.5 pF
  • 4 4 * 2.5 pF = 10 pF
  • 5 5 * 2.5 pF = 12.5 pF
  • 6 6 * 2.5 pF = 15 pF
  • 7 7 * 2.5 pF = 17.5 pF
SAMC25:16Sample Time for the Shared ADC bits
  • 0 2 Tad7
  • 1 3 Tad7
  • 1023 1025 Tad7
BGVRIEN15Band Gap/VREF Voltage Ready Interrupt Enable bit
  • 0 No interrupt is generated when the BGVRRDY bit is set
  • 1 Interrupt will be generated when the BGVRDDY bit is set
REFFLTIEN14Band Gap/VREF Voltage Fault Interrupt Enable bit
  • 0 No interrupt is generated when the REFFLT bit is set
  • 1 Interrupt will be generated when the REFFLT bit is set
EOSIEN13End of Scan Interrupt Enable bit
  • 0 No interrupt is generated when the EOSRDY bit is set
  • 1 Interrupt will be generated when EOSRDY bit is set
ADCEIOVR12Early Interrupt Request Override bit
  • 0 Early interrupt generation is overridden and interrupt generation is controlled by the ADCGIRQEN1 and ADCGIRQEN2 registers
  • 1 Early interrupt generation is not overridden and interrupt generation is controlled by the ADCEIEN1 and ADCEIEN2 registers
ADCEIS10:8Shared ADC Early Interrupt Select bits
  • 0 The data ready interrupt is generated 1 ADC module clock prior to end of conversion
  • 1 The data ready interrupt is generated 2 ADC module clocks prior to end of conversion
  • 6 The data ready interrupt is generated 7 ADC clocks prior to end of conversion
  • 7 The data ready interrupt is generated 8 ADC clocks prior to end of conversion
ADCDIV6:0Shared ADC Clock Divider bits
  • 0 Reserved
  • 1 2 * Tq = Tad7
  • 2 4 * Tq = Tad7
  • 3 6 * Tq = Tad7
  • 127 254 * Tq = Tad7
BGVRRDY31Band Gap Voltage/ADC Reference Voltage Status bit
  • 0 Either or both band gap voltage and ADC reference voltages (Vref) are not ready
  • 1 Both band gap voltage and ADC reference voltages (Vref) are ready

ADCCON3ADC Control Register 3

Address
0xBF84B008
Reset
0x00000000
Access
read/write
Size
32-bit
17 fields
FieldBitsWhat it does
CONCLKDIV29:24Analog-to-Digital Control Clock Divider bits
  • 0 Tclk = Tq
  • 1 2 * Tclk = Tq
  • 2 3 * Tclk = Tq
  • 3 4 * Tclk = Tq
  • 63 64 * Tclk = Tq
DIGEN723Shared ADC Digital Enable bit
  • 0 ADC7 is digital disabled
  • 1 ADC7 is digital enabled
DIGEN420ADC4 Digital Enable bit
  • 0 ADC4 is digital disabled
  • 1 ADC4 is digital enabled
DIGEN319ADC3 Digital Enable bit
  • 0 ADC3 is digital disabled
  • 1 ADC3 is digital enabled
DIGEN218ADC2 Digital Enable bit
  • 0 ADC2 is digital disabled
  • 1 ADC2 is digital enabled
DIGEN117ADC1 Digital Enable bit
  • 0 ADC1 is digital disabled
  • 1 ADC1 is digital enabled
DIGEN016ADC0 Digital Enable bit
  • 0 ADC0 is digital disabled
  • 1 ADC0 is digital enabled
VREFSEL15:13Voltage Reference Input Selection bits
  • 0 External AVDD and AVSS
  • 1 External VREFH and AVSS
  • 2 AVDD and External VREFL
  • 3 External VREFH and External VREFL
  • 4 Reserved
  • 5 Reserved
  • 6 Reserved
  • 7 Reserved
TRGSUSP12Trigger Suspend bit
  • 0 Triggers are not blocked
  • 1 Triggers are blocked from starting a new analog-to-digital conversion
UPDIEN11Update Ready Interrupt Enable bit
  • 0 No interrupt is generated
  • 1 Interrupt will be generated when the UPDRDY bit is set by hardware
UPDRDY10ADC Update Ready Status bit
  • 0 ADC SFRs cannot be updated
  • 1 ADC SFRs can be updated
SAMP9Class 2 and Class 3 Analog Input Sampling Enable bit
  • 0 The ADC S&H amplifier is holding
  • 1 The ADC S&H amplifier is sampling
RQCNVRT8Individual ADC Input Conversion Request bit
  • 0 Do not trigger the conversion
  • 1 Trigger the conversion of the selected ADC input as specified by the ADINSEL bits
GLSWTRG7Global Level Software Trigger bit
  • 0 Do not trigger an analog-to-digital conversion
  • 1 Trigger conversion for ADC inputs that have selected the GLSWTRG bit as the trigger signal
GSWTRG6Global Software Trigger bit
  • 0 Do not trigger an analog-to-digital conversion
  • 1 Trigger conversion for ADC inputs that have selected the GSWTRG bit as the trigger signal
ADINSEL5:0Analog Input Select bits
  • 0 AN0
  • 1 AN1
  • 42 MAX_AN_INPUT = AN[MAX_AN_INPUT]
  • 43 MAX_AN_INPUT + 1 = IVREF
  • 44 MAX_AN_INPUT + 2 = IVTEMP
  • 45 Reserved
  • 63 Reserved
ADCSEL31:30Analog-to-Digital Clock Source bits
  • 0 PBCLK3
  • 1 System Clock (Tcy)
  • 2 REFCLK3
  • 3 FRC

ADCTRGMODEADC Triggering Mode for Dedicated ADC Register

Address
0xBF84B00C
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
SH4ALT25:24ADC4 Analog Input Select bit
  • 0 AN4
  • 1 AN49
  • 2 Reserved
  • 3 Reserved
SH3ALT23:22ADC3 Analog Input Select bit
  • 0 AN3
  • 1 AN48
  • 2 Reserved
  • 3 Reserved
SH2ALT21:20ADC2 Analog Input Select bit
  • 0 AN2
  • 1 AN47
  • 2 Reserved
  • 3 Reserved
SH1ALT19:18ADC1 Analog Input Select bit
  • 0 AN1
  • 1 AN46
  • 2 Reserved
  • 3 Reserved
SH0ALT17:16ADC0 Analog Input Select bit
  • 0 AN0
  • 1 AN45
  • 2 Reserved
  • 3 Reserved
STRGEN412ADC4 Presynchronized Triggers bit
  • 0 ADC4 does not use presynchronized triggers
  • 1 ADC4 uses presynchronized triggers
STRGEN311ADC3 Presynchronized Triggers bit
  • 0 ADC3 does not use presynchronized triggers
  • 1 ADC3 uses presynchronized triggers
STRGEN210ADC2 Presynchronized Triggers bit
  • 0 ADC2 does not use presynchronized triggers
  • 1 ADC2 uses presynchronized triggers
STRGEN19ADC1 Presynchronized Triggers bit
  • 0 ADC1 does not use presynchronized triggers
  • 1 ADC1 uses presynchronized triggers
STRGEN08ADC0 Presynchronized Triggers bit
  • 0 ADC0 does not use presynchronized triggers
  • 1 ADC0 uses presynchronized triggers
SSAMPEN44ADC4 Synchronous Sampling bit
  • 0 ADC4 does not use synchronous sampling
  • 1 ADC4 uses synchronous sampling for the first sample after being idle or disabled
SSAMPEN33ADC3 Synchronous Sampling bit
  • 0 ADC3 does not use synchronous sampling
  • 1 ADC3 uses synchronous sampling for the first sample after being idle or disabled
SSAMPEN22ADC2Synchronous Sampling bit
  • 0 ADC2 does not use synchronous sampling
  • 1 ADC2 uses synchronous sampling for the first sample after being idle or disabled
SSAMPEN11ADC1 Synchronous Sampling bit
  • 0 ADC1 does not use synchronous sampling
  • 1 ADC1 uses synchronous sampling for the first sample after being idle or disabled
SSAMPEN00ADC0 Synchronous Sampling bit
  • 0 ADC0 does not use synchronous sampling
  • 1 ADC0 uses synchronous sampling for the first sample after being idle or disabled

ADCIMCON1ADC Input Mode Control Register 1

Address
0xBF84B010
Reset
0x00000000
Access
read/write
Size
32-bit
32 fields
FieldBitsWhat it does
SIGN1530AN15 Signed Data Mode bit
  • 0 AN15 is using Unsigned Data mode
  • 1 AN15 is using Signed Data mode
DIFF1429AN14 Mode bit
  • 0 AN14 is using Single-ended mode
  • 1 AN14 is using Differential mode
SIGN1428AN14 Signed Data Mode bit
  • 0 AN14 is using Unsigned Data mode
  • 1 AN14 is using Signed Data mode
DIFF1327AN13 Mode bit
  • 0 AN13 is using Single-ended mode
  • 1 AN13 is using Differential mode
SIGN1326AN13 Signed Data Mode bit
  • 0 AN13 is using Unsigned Data mode
  • 1 AN13 is using Signed Data mode
DIFF1225AN12 Mode bit
  • 0 AN12 is using Single-ended mode
  • 1 AN12 is using Differential mode
SIGN1224AN12 Signed Data Mode bit
  • 0 AN12 is using Unsigned Data mode
  • 1 AN12 is using Signed Data mode
DIFF1123AN11 Mode bit
  • 0 AN11 is using Single-ended mode
  • 1 AN11 is using Differential mode
SIGN1122AN11 Signed Data Mode bit
  • 0 AN11 is using Unsigned Data mode
  • 1 AN11 is using Signed Data mode
DIFF1021AN10 Mode bit
  • 0 AN10 is using Single-ended mode
  • 1 AN10 is using Differential mode
SIGN1020AN10 Signed Data Mode bit
  • 0 AN10 is using Unsigned Data mode
  • 1 AN10 is using Signed Data mode
DIFF919AN9 Mode bit
  • 0 AN9 is using Single-ended mode
  • 1 AN9 is using Differential mode
SIGN918AN9 Signed Data Mode bit
  • 0 AN9 is using Unsigned Data mode
  • 1 AN9 is using Signed Data mode
DIFF817AN 8 Mode bit
  • 0 AN8 is using Single-ended mode
  • 1 AN8 is using Differential mode
SIGN816AN8 Signed Data Mode bit
  • 0 AN8 is using Unsigned Data mode
  • 1 AN8 is using Signed Data mode
DIFF715AN7 Mode bit
  • 0 AN7 is using Single-ended mode
  • 1 AN7 is using Differential mode
SIGN714AN7 Signed Data Mode bit
  • 0 AN7 is using Unsigned Data mode
  • 1 AN7 is using Signed Data mode
DIFF613AN6 Mode bit
  • 0 AN6 is using Single-ended mode
  • 1 AN6 is using Differential mode
SIGN612AN6 Signed Data Mode bit
  • 0 AN6 is using Unsigned Data mode
  • 1 AN6 is using Signed Data mode
DIFF511AN5 Mode bit
  • 0 AN5 is using Single-ended mode
  • 1 AN5 is using Differential mode
SIGN510AN5 Signed Data Mode bit
  • 0 AN5 is using Unsigned Data mode
  • 1 AN5 is using Signed Data mode
DIFF49AN4 Mode bit
  • 0 AN4 is using Single-ended mode
  • 1 AN4 is using Differential mode
SIGN48AN4 Signed Data Mode bit
  • 0 AN4 is using Unsigned Data mode
  • 1 AN4 is using Signed Data mode
DIFF37AN3 Mode bit
  • 0 AN3 is using Single-ended mode
  • 1 AN3 is using Differential mode
SIGN36AN3 Signed Data Mode bit
  • 0 AN3 is using Unsigned Data mode
  • 1 AN3 is using Signed Data mode
DIFF25AN2 Mode bit
  • 0 AN2 is using Single-ended mode
  • 1 AN2 is using Differential mode
SIGN24AN2 Signed Data Mode bit
  • 0 AN2 is using Unsigned Data mode
  • 1 AN2 is using Signed Data mode
DIFF13AN1 Mode bit
  • 0 AN1 is using Single-ended mode
  • 1 AN1 is using Differential mode
SIGN12AN1 Signed Data Mode bit
  • 0 AN1 is using Unsigned Data mode
  • 1 AN1 is using Signed Data mode
DIFF01AN0 Mode bit
  • 0 AN0 is using Single-ended mode
  • 1 AN0 is using Differential mode
SIGN00AN0 Signed Data Mode bit
  • 0 AN0 is using Unsigned Data mode
  • 1 AN0 is using Signed Data mode
DIFF1531AN15 Mode bit
  • 0 AN15 is using Single-ended mode
  • 1 AN15 is using Differential mode

ADCIMCON2ADC Input Mode Control Register 2

Address
0xBF84B014
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
DIFF185AN18 Mode bit
  • 0 AN18 is using Single-ended mode
  • 1 AN18 is using Differential mode
SIGN184AN18 Signed Data Mode bit
  • 0 AN18 is using Unsigned Data mode
  • 1 AN18 is using Signed Data mode
DIFF173AN17 Mode bit
  • 0 AN17 is using Single-ended mode
  • 1 AN17 is using Differential mode
SIGN172AN17 Signed Data Mode bit
  • 0 AN17 is using Unsigned Data mode
  • 1 AN17 is using Signed Data mode
DIFF161AN16 Mode bit
  • 0 AN16 is using Single-ended mode
  • 1 AN16 is using Differential mode
SIGN160AN16 Signed Data Mode bit
  • 0 AN16 is using Unsigned Data mode
  • 1 AN16 is using Signed Data mode

ADCIMCON3ADC Input Mode Control Register 3

Address
0xBF84B018
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
DIFF4425AN44 Mode bit
  • 0 AN44 is using Single-ended mode
  • 1 AN44 is using Differential mode
SIGN4424AN44 Signed Data Mode bit
  • 0 AN44 is using Unsigned Data mode
  • 1 AN44 is using Signed Data mode
DIFF4323AN43 Mode bit
  • 0 AN43 is using Single-ended mode
  • 1 AN43 is using Differential mode
SIGN4322AN43 Signed Data Mode bit
  • 0 AN43 is using Unsigned Data mode
  • 1 AN43 is using Signed Data mode

ADCGIRQEN1ADC Global Interrupt Enable Register 1

Address
0xBF84B020
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
AGIEN1818ADC Global Interrupt Enable bits for analog input 18
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)
AGIEN1717ADC Global Interrupt Enable bits for analog input 17
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)
AGIEN1616ADC Global Interrupt Enable bits for analog input 16
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)
AGIEN1515ADC Global Interrupt Enable bits for analog input 15
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)
AGIEN1414ADC Global Interrupt Enable bits for analog input 14
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)
AGIEN1313ADC Global Interrupt Enable bits for analog input 13
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)
AGIEN1212ADC Global Interrupt Enable bits for analog input 12
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)
AGIEN1111ADC Global Interrupt Enable bits for analog input 11
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)
AGIEN1010ADC Global Interrupt Enable bits for analog input 10
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)
AGIEN99ADC Global Interrupt Enable bits for analog input 9
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)
AGIEN88ADC Global Interrupt Enable bits for analog input 8
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)
AGIEN77ADC Global Interrupt Enable bits for analog input 7
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)
AGIEN66ADC Global Interrupt Enable bits for analog input 6
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)
AGIEN55ADC Global Interrupt Enable bits for analog input 5
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)
AGIEN44ADC Global Interrupt Enable bits for analog input 4
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)
AGIEN33ADC Global Interrupt Enable bits for analog input 3
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)
AGIEN22ADC Global Interrupt Enable bits for analog input 2
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)
AGIEN11ADC Global Interrupt Enable bits for analog input 1
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)
AGIEN00ADC Global Interrupt Enable bits for analog input 0
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)

ADCGIRQEN2ADC Global Interrupt Enable Register 2

Address
0xBF84B024
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
AGIEN4412ADC Global Interrupt Enable bits for analog input 44
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)
AGIEN4311ADC Global Interrupt Enable bits for analog input 43
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)

ADCCSS1ADC Common Scan Select Register 1

Address
0xBF84B028
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
CSS1818Analog Common Scan Select bits 18
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan
CSS1717Analog Common Scan Select bits 17
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan
CSS1616Analog Common Scan Select bits 16
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan
CSS1515Analog Common Scan Select bits 15
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan
CSS1414Analog Common Scan Select bits 14
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan
CSS1313Analog Common Scan Select bits 13
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan
CSS1212Analog Common Scan Select bits 12
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan
CSS1111Analog Common Scan Select bits 11
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan
CSS1010Analog Common Scan Select bits 10
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan
CSS99Analog Common Scan Select bits 9
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan
CSS88Analog Common Scan Select bits 8
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan
CSS77Analog Common Scan Select bits 7
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan
CSS66Analog Common Scan Select bits 6
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan
CSS55Analog Common Scan Select bits 5
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan
CSS44Analog Common Scan Select bits 4
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan
CSS33Analog Common Scan Select bits 3
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan
CSS22Analog Common Scan Select bits 2
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan
CSS11Analog Common Scan Select bits 1
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan
CSS00Analog Common Scan Select bits 0
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan

ADCCSS2ADC Common Scan Select Register 2

Address
0xBF84B02C
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
CSS4412Analog Common Scan Select bits 44
  • 0 Skip ANx for input scan
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan
  • 1 Select ANx for input scan
CSS4311Analog Common Scan Select bits 43
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan

ADCDSTAT1ADC Data Ready Status Register 1

Address
0xBF84B030
Reset
0x00000000
Access
read only
Size
32-bit
19 fields
FieldBitsWhat it does
ARDY1818Conversion Data Ready for Corresponding Analog Input Ready bit 18
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY1717Conversion Data Ready for Corresponding Analog Input Ready bit 17
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY1616Conversion Data Ready for Corresponding Analog Input Ready bit 16
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY1515Conversion Data Ready for Corresponding Analog Input Ready bit 15
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY1414Conversion Data Ready for Corresponding Analog Input Ready bit 14
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY1313Conversion Data Ready for Corresponding Analog Input Ready bit 13
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY1212Conversion Data Ready for Corresponding Analog Input Ready bit 12
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY1111Conversion Data Ready for Corresponding Analog Input Ready bit 11
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY1010Conversion Data Ready for Corresponding Analog Input Ready bit 10
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY99Conversion Data Ready for Corresponding Analog Input Ready bit 9
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY88Conversion Data Ready for Corresponding Analog Input Ready bit 8
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY77Conversion Data Ready for Corresponding Analog Input Ready bit 7
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY66Conversion Data Ready for Corresponding Analog Input Ready bit 6
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY55Conversion Data Ready for Corresponding Analog Input Ready bit 5
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY44Conversion Data Ready for Corresponding Analog Input Ready bit 4
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY33Conversion Data Ready for Corresponding Analog Input Ready bit 3
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY22Conversion Data Ready for Corresponding Analog Input Ready bit 2
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY11Conversion Data Ready for Corresponding Analog Input Ready bit 1
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY00Conversion Data Ready for Corresponding Analog Input Ready bit 0
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register

ADCDSTAT2ADC Data Ready Status Register 2

Address
0xBF84B034
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
ARDY4412Conversion Data Ready for Corresponding Analog Input Ready bit 44
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY4311Conversion Data Ready for Corresponding Analog Input Ready bit 43
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register

ADCCMPEN1ADC Digital Comparator x Enable Register (x = 1 through 6)

Address
0xBF84B038
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
CMPE1818
CMPE1717
CMPE1616
CMPE1515
CMPE1414
CMPE1313
CMPE1212
CMPE1111
CMPE1010
CMPE99
CMPE88
CMPE77
CMPE66
CMPE55
CMPE44
CMPE33
CMPE22
CMPE11
CMPE00

ADCCMP1ADC Digital Comparator x Limit Value Register (x = 1 through 6)

Address
0xBF84B03C
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
DCMPLO15:0
DCMPHI31:16

ADCCMPEN2ADC Digital Comparator x Enable Register (x = 1 through 6)

Address
0xBF84B040
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
CMPE1818
CMPE1717
CMPE1616
CMPE1515
CMPE1414
CMPE1313
CMPE1212
CMPE1111
CMPE1010
CMPE99
CMPE88
CMPE77
CMPE66
CMPE55
CMPE44
CMPE33
CMPE22
CMPE11
CMPE00

ADCCMP2ADC Digital Comparator x Limit Value Register (x = 1 through 6)

Address
0xBF84B044
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
DCMPLO15:0
DCMPHI31:16

ADCCMPEN3ADC Digital Comparator x Enable Register (x = 1 through 6)

Address
0xBF84B048
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
CMPE1818
CMPE1717
CMPE1616
CMPE1515
CMPE1414
CMPE1313
CMPE1212
CMPE1111
CMPE1010
CMPE99
CMPE88
CMPE77
CMPE66
CMPE55
CMPE44
CMPE33
CMPE22
CMPE11
CMPE00

ADCCMP3ADC Digital Comparator x Limit Value Register (x = 1 through 6)

Address
0xBF84B04C
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
DCMPLO15:0
DCMPHI31:16

ADCCMPEN4ADC Digital Comparator x Enable Register (x = 1 through 6)

Address
0xBF84B050
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
CMPE1818
CMPE1717
CMPE1616
CMPE1515
CMPE1414
CMPE1313
CMPE1212
CMPE1111
CMPE1010
CMPE99
CMPE88
CMPE77
CMPE66
CMPE55
CMPE44
CMPE33
CMPE22
CMPE11
CMPE00

ADCCMP4ADC Digital Comparator x Limit Value Register (x = 1 through 6)

Address
0xBF84B054
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
DCMPLO15:0
DCMPHI31:16

ADCCMPEN5ADC Digital Comparator x Enable Register (x = 1 through 6)

Address
0xBF84B058
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
CMPE1818
CMPE1717
CMPE1616
CMPE1515
CMPE1414
CMPE1313
CMPE1212
CMPE1111
CMPE1010
CMPE99
CMPE88
CMPE77
CMPE66
CMPE55
CMPE44
CMPE33
CMPE22
CMPE11
CMPE00

ADCCMP5ADC Digital Comparator x Limit Value Register (x = 1 through 6)

Address
0xBF84B05C
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
DCMPLO15:0
DCMPHI31:16

ADCCMPEN6ADC Digital Comparator x Enable Register (x = 1 through 6)

Address
0xBF84B060
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
CMPE1818
CMPE1717
CMPE1616
CMPE1515
CMPE1414
CMPE1313
CMPE1212
CMPE1111
CMPE1010
CMPE99
CMPE88
CMPE77
CMPE66
CMPE55
CMPE44
CMPE33
CMPE22
CMPE11
CMPE00

ADCCMP6ADC Digital Comparator x Limit Value Register (x = 1 through 6)

Address
0xBF84B064
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
DCMPLO15:0
DCMPHI31:16

ADCFLTR1ADC Digital Filter x Register (x = 1 through 6)

Address
0xBF84B068
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
DATA16EN30Filter Significant Data Length bit
  • 0 Only the first 12 bits are significant
  • 1 All 16 bits of the filter output data are significant
DFMODE29ADC Filter Mode bit
  • 0 Filter x works in Oversampling Filter mode (default)
  • 1 Filter x works in Averaging mode
OVRSAM28:26Oversampling Filter Ratio bits
  • 0 (If DFMODE is 0) 4 samples (shift sum 1 bit to right
  • 1 (If DFMODE is 0) 16 samples (shift sum 2 bits to right
  • 2 (If DFMODE is 0) 64 samples (shift sum 3 bits to right
  • 3 (If DFMODE is 0) 256 samples (shift sum 4 bits to right
  • 4 (If DFMODE is 0) 2 samples (shift sum 0 bits to right
  • 5 (If DFMODE is 0) 8 samples (shift sum 1 bit to right
  • 6 (If DFMODE is 0) 32 samples (shift sum 2 bits to right
  • 7 (If DFMODE is 0) 128 samples (shift sum 3 bits to right
AFGIEN25Digital Filter x Interrupt Enable bit
  • 0 Digital filter is disabled
  • 1 Digital filter interrupt is enabled and is generated by the AFRDY status bit
AFRDY24Digital Filter x Data Ready Status bit
  • 0 Data is not ready
  • 1 Data is ready in the FLTRDATA bits
CHNLID20:16Digital Filter Analog Input Selection bits
  • 0 AN0
  • 1 AN1
  • 2 AN2
  • 11 AN11
  • 12 Reserved
  • 31 Reserved
FLTRDATA15:0
AFEN31Digital Filter x Enable bit
  • 0 Digital filter is disabled and the AFRDY status bit is cleared
  • 1 Digital filter is enabled

ADCFLTR2ADC Digital Filter x Register (x = 1 through 6)

Address
0xBF84B06C
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
DATA16EN30Filter Significant Data Length bit
  • 0 Only the first 12 bits are significant
  • 1 All 16 bits of the filter output data are significant
DFMODE29ADC Filter Mode bit
  • 0 Filter x works in Oversampling Filter mode (default)
  • 1 Filter x works in Averaging mode
OVRSAM28:26Oversampling Filter Ratio bits
  • 0 (If DFMODE is 0) 4 samples (shift sum 1 bit to right
  • 1 (If DFMODE is 0) 16 samples (shift sum 2 bits to right
  • 2 (If DFMODE is 0) 64 samples (shift sum 3 bits to right
  • 3 (If DFMODE is 0) 256 samples (shift sum 4 bits to right
  • 4 (If DFMODE is 0) 2 samples (shift sum 0 bits to right
  • 5 (If DFMODE is 0) 8 samples (shift sum 1 bit to right
  • 6 (If DFMODE is 0) 32 samples (shift sum 2 bits to right
  • 7 (If DFMODE is 0) 128 samples (shift sum 3 bits to right
AFGIEN25Digital Filter x Interrupt Enable bit
  • 0 Digital filter is disabled
  • 1 Digital filter interrupt is enabled and is generated by the AFRDY status bit
AFRDY24Digital Filter x Data Ready Status bit
  • 0 Data is not ready
  • 1 Data is ready in the FLTRDATA bits
CHNLID20:16Digital Filter Analog Input Selection bits
  • 0 AN0
  • 1 AN1
  • 2 AN2
  • 11 AN11
  • 12 Reserved
  • 31 Reserved
FLTRDATA15:0
AFEN31Digital Filter x Enable bit
  • 0 Digital filter is disabled and the AFRDY status bit is cleared
  • 1 Digital filter is enabled

ADCFLTR3ADC Digital Filter x Register (x = 1 through 6)

Address
0xBF84B070
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
DATA16EN30Filter Significant Data Length bit
  • 0 Only the first 12 bits are significant
  • 1 All 16 bits of the filter output data are significant
DFMODE29ADC Filter Mode bit
  • 0 Filter x works in Oversampling Filter mode (default)
  • 1 Filter x works in Averaging mode
OVRSAM28:26Oversampling Filter Ratio bits
  • 0 (If DFMODE is 0) 4 samples (shift sum 1 bit to right
  • 1 (If DFMODE is 0) 16 samples (shift sum 2 bits to right
  • 2 (If DFMODE is 0) 64 samples (shift sum 3 bits to right
  • 3 (If DFMODE is 0) 256 samples (shift sum 4 bits to right
  • 4 (If DFMODE is 0) 2 samples (shift sum 0 bits to right
  • 5 (If DFMODE is 0) 8 samples (shift sum 1 bit to right
  • 6 (If DFMODE is 0) 32 samples (shift sum 2 bits to right
  • 7 (If DFMODE is 0) 128 samples (shift sum 3 bits to right
AFGIEN25Digital Filter x Interrupt Enable bit
  • 0 Digital filter is disabled
  • 1 Digital filter interrupt is enabled and is generated by the AFRDY status bit
AFRDY24Digital Filter x Data Ready Status bit
  • 0 Data is not ready
  • 1 Data is ready in the FLTRDATA bits
CHNLID20:16Digital Filter Analog Input Selection bits
  • 0 AN0
  • 1 AN1
  • 2 AN2
  • 11 AN11
  • 12 Reserved
  • 31 Reserved
FLTRDATA15:0
AFEN31Digital Filter x Enable bit
  • 0 Digital filter is disabled and the AFRDY status bit is cleared
  • 1 Digital filter is enabled

ADCFLTR4ADC Digital Filter x Register (x = 1 through 6)

Address
0xBF84B074
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
DATA16EN30Filter Significant Data Length bit
  • 0 Only the first 12 bits are significant
  • 1 All 16 bits of the filter output data are significant
DFMODE29ADC Filter Mode bit
  • 0 Filter x works in Oversampling Filter mode (default)
  • 1 Filter x works in Averaging mode
OVRSAM28:26Oversampling Filter Ratio bits
  • 0 (If DFMODE is 0) 4 samples (shift sum 1 bit to right
  • 1 (If DFMODE is 0) 16 samples (shift sum 2 bits to right
  • 2 (If DFMODE is 0) 64 samples (shift sum 3 bits to right
  • 3 (If DFMODE is 0) 256 samples (shift sum 4 bits to right
  • 4 (If DFMODE is 0) 2 samples (shift sum 0 bits to right
  • 5 (If DFMODE is 0) 8 samples (shift sum 1 bit to right
  • 6 (If DFMODE is 0) 32 samples (shift sum 2 bits to right
  • 7 (If DFMODE is 0) 128 samples (shift sum 3 bits to right
AFGIEN25Digital Filter x Interrupt Enable bit
  • 0 Digital filter is disabled
  • 1 Digital filter interrupt is enabled and is generated by the AFRDY status bit
AFRDY24Digital Filter x Data Ready Status bit
  • 0 Data is not ready
  • 1 Data is ready in the FLTRDATA bits
CHNLID20:16Digital Filter Analog Input Selection bits
  • 0 AN0
  • 1 AN1
  • 2 AN2
  • 11 AN11
  • 12 Reserved
  • 31 Reserved
FLTRDATA15:0
AFEN31Digital Filter x Enable bit
  • 0 Digital filter is disabled and the AFRDY status bit is cleared
  • 1 Digital filter is enabled

ADCFLTR5ADC Digital Filter x Register (x = 1 through 6)

Address
0xBF84B078
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
DATA16EN30Filter Significant Data Length bit
  • 0 Only the first 12 bits are significant
  • 1 All 16 bits of the filter output data are significant
DFMODE29ADC Filter Mode bit
  • 0 Filter x works in Oversampling Filter mode (default)
  • 1 Filter x works in Averaging mode
OVRSAM28:26Oversampling Filter Ratio bits
  • 0 (If DFMODE is 0) 4 samples (shift sum 1 bit to right
  • 1 (If DFMODE is 0) 16 samples (shift sum 2 bits to right
  • 2 (If DFMODE is 0) 64 samples (shift sum 3 bits to right
  • 3 (If DFMODE is 0) 256 samples (shift sum 4 bits to right
  • 4 (If DFMODE is 0) 2 samples (shift sum 0 bits to right
  • 5 (If DFMODE is 0) 8 samples (shift sum 1 bit to right
  • 6 (If DFMODE is 0) 32 samples (shift sum 2 bits to right
  • 7 (If DFMODE is 0) 128 samples (shift sum 3 bits to right
AFGIEN25Digital Filter x Interrupt Enable bit
  • 0 Digital filter is disabled
  • 1 Digital filter interrupt is enabled and is generated by the AFRDY status bit
AFRDY24Digital Filter x Data Ready Status bit
  • 0 Data is not ready
  • 1 Data is ready in the FLTRDATA bits
CHNLID20:16Digital Filter Analog Input Selection bits
  • 0 AN0
  • 1 AN1
  • 2 AN2
  • 11 AN11
  • 12 Reserved
  • 31 Reserved
FLTRDATA15:0
AFEN31Digital Filter x Enable bit
  • 0 Digital filter is disabled and the AFRDY status bit is cleared
  • 1 Digital filter is enabled

ADCFLTR6ADC Digital Filter x Register (x = 1 through 6)

Address
0xBF84B07C
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
DATA16EN30Filter Significant Data Length bit
  • 0 Only the first 12 bits are significant
  • 1 All 16 bits of the filter output data are significant
DFMODE29ADC Filter Mode bit
  • 0 Filter x works in Oversampling Filter mode (default)
  • 1 Filter x works in Averaging mode
OVRSAM28:26Oversampling Filter Ratio bits
  • 0 (If DFMODE is 0) 4 samples (shift sum 1 bit to right
  • 1 (If DFMODE is 0) 16 samples (shift sum 2 bits to right
  • 2 (If DFMODE is 0) 64 samples (shift sum 3 bits to right
  • 3 (If DFMODE is 0) 256 samples (shift sum 4 bits to right
  • 4 (If DFMODE is 0) 2 samples (shift sum 0 bits to right
  • 5 (If DFMODE is 0) 8 samples (shift sum 1 bit to right
  • 6 (If DFMODE is 0) 32 samples (shift sum 2 bits to right
  • 7 (If DFMODE is 0) 128 samples (shift sum 3 bits to right
AFGIEN25Digital Filter x Interrupt Enable bit
  • 0 Digital filter is disabled
  • 1 Digital filter interrupt is enabled and is generated by the AFRDY status bit
AFRDY24Digital Filter x Data Ready Status bit
  • 0 Data is not ready
  • 1 Data is ready in the FLTRDATA bits
CHNLID20:16Digital Filter Analog Input Selection bits
  • 0 AN0
  • 1 AN1
  • 2 AN2
  • 11 AN11
  • 12 Reserved
  • 31 Reserved
FLTRDATA15:0
AFEN31Digital Filter x Enable bit
  • 0 Digital filter is disabled and the AFRDY status bit is cleared
  • 1 Digital filter is enabled

ADCTRG1ADC Trigger Source 1 Register

Address
0xBF84B080
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TRGSRC328:24Trigger Source for Conversion of Analog Input AN3 Select bits
  • 0 No Trigger
  • 1 Global software edge Trigger (GSWTRG)
  • 2 Global level software trigger (GLSWTRG)
  • 3 STRIG
  • 4 INT0 External interrupt
  • 5 TMR1 match
  • 6 TMR3 match
  • 7 TMR5 match
  • 8 OCMP1
  • 9 OCMP3
  • 10 OCMP5
  • 11 Comparator 1 (COUT)
  • 12 Comparator 2 (COUT)
  • 13 Reserved
  • 31 Reserved
TRGSRC220:16Trigger Source for Conversion of Analog Input AN2 Select
  • 0 No Trigger
  • 1 Global software edge Trigger (GSWTRG)
  • 2 Global level software trigger (GLSWTRG)
  • 3 STRIG
  • 4 INT0 External interrupt
  • 5 TMR1 match
  • 6 TMR3 match
  • 7 TMR5 match
  • 8 OCMP1
  • 9 OCMP3
  • 10 OCMP5
  • 11 Comparator 1 (COUT)
  • 12 Comparator 2 (COUT)
  • 13 Reserved
  • 31 Reserved
TRGSRC112:8Trigger Source for Conversion of Analog Input AN1 Select bits
  • 0 No Trigger
  • 1 Global software edge Trigger (GSWTRG)
  • 2 Global level software trigger (GLSWTRG)
  • 3 STRIG
  • 4 INT0 External interrupt
  • 5 TMR1 match
  • 6 TMR3 match
  • 7 TMR5 match
  • 8 OCMP1
  • 9 OCMP3
  • 10 OCMP5
  • 11 Comparator 1 (COUT)
  • 12 Comparator 2 (COUT)
  • 13 Reserved
  • 31 Reserved
TRGSRC04:0Trigger Source for Conversion of Analog Input AN0 Select bits
  • 0 No Trigger
  • 1 Global software edge Trigger (GSWTRG)
  • 2 Global level software trigger (GLSWTRG)
  • 3 STRIG
  • 4 INT0 External interrupt
  • 5 TMR1 match
  • 6 TMR3 match
  • 7 TMR5 match
  • 8 OCMP1
  • 9 OCMP3
  • 10 OCMP5
  • 11 Comparator 1 (COUT)
  • 12 Comparator 2 (COUT)
  • 13 Reserved
  • 31 Reserved

ADCTRG2ADC Trigger Source 2 Register

Address
0xBF84B084
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TRGSRC728:24Trigger Source for Conversion of Analog Input AN7 Select bits
  • 0 No Trigger
  • 1 Global software edge Trigger (GSWTRG)
  • 2 Global level software trigger (GLSWTRG)
  • 3 STRIG
  • 4 INT0 External interrupt
  • 5 TMR1 match
  • 6 TMR3 match
  • 7 TMR5 match
  • 8 OCMP1
  • 9 OCMP3
  • 10 OCMP5
  • 11 Comparator 1 (COUT)
  • 12 Comparator 2 (COUT)
  • 13 Reserved
  • 31 Reserved
TRGSRC620:16Trigger Source for Conversion of Analog Input AN6 Select bits
  • 0 No Trigger
  • 1 Global software edge Trigger (GSWTRG)
  • 2 Global level software trigger (GLSWTRG)
  • 3 STRIG
  • 4 INT0 External interrupt
  • 5 TMR1 match
  • 6 TMR3 match
  • 7 TMR5 match
  • 8 OCMP1
  • 9 OCMP3
  • 10 OCMP5
  • 11 Comparator 1 (COUT)
  • 12 Comparator 2 (COUT)
  • 13 Reserved
  • 31 Reserved
TRGSRC512:8Trigger Source for Conversion of Analog Input AN5 Select bits
  • 0 No Trigger
  • 1 Global software edge Trigger (GSWTRG)
  • 2 Global level software trigger (GLSWTRG)
  • 3 STRIG
  • 4 INT0 External interrupt
  • 5 TMR1 match
  • 6 TMR3 match
  • 7 TMR5 match
  • 8 OCMP1
  • 9 OCMP3
  • 10 OCMP5
  • 11 Comparator 1 (COUT)
  • 12 Comparator 2 (COUT)
  • 13 Reserved
  • 31 Reserved
TRGSRC44:0Trigger Source for Conversion of Analog Input AN4 Select bits
  • 0 No Trigger
  • 1 Global software edge Trigger (GSWTRG)
  • 2 Global level software trigger (GLSWTRG)
  • 3 STRIG
  • 4 INT0 External interrupt
  • 5 TMR1 match
  • 6 TMR3 match
  • 7 TMR5 match
  • 8 OCMP1
  • 9 OCMP3
  • 10 OCMP5
  • 11 Comparator 1 (COUT)
  • 12 Comparator 2 (COUT)
  • 13 Reserved
  • 31 Reserved

ADCTRG3ADC Trigger Source 3 Register

Address
0xBF84B088
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TRGSRC1128:24Trigger Source for Conversion of Analog Input AN11 Select bits
  • 0 No Trigger
  • 1 Global software edge Trigger (GSWTRG)
  • 2 Global level software trigger (GLSWTRG)
  • 3 STRIG
  • 4 INT0 External interrupt
  • 5 TMR1 match
  • 6 TMR3 match
  • 7 TMR5 match
  • 8 OCMP1
  • 9 OCMP3
  • 10 OCMP5
  • 11 Comparator 1 (COUT)
  • 12 Comparator 2 (COUT)
  • 13 Reserved
  • 31 Reserved
TRGSRC1020:16Trigger Source for Conversion of Analog Input AN10 Select bits
  • 0 No Trigger
  • 1 Global software edge Trigger (GSWTRG)
  • 2 Global level software trigger (GLSWTRG)
  • 3 STRIG
  • 4 INT0 External interrupt
  • 5 TMR1 match
  • 6 TMR3 match
  • 7 TMR5 match
  • 8 OCMP1
  • 9 OCMP3
  • 10 OCMP5
  • 11 Comparator 1 (COUT)
  • 12 Comparator 2 (COUT)
  • 13 Reserved
  • 31 Reserved
TRGSRC912:8Trigger Source for Conversion of Analog Input AN9 Select bits
  • 0 No Trigger
  • 1 Global software edge Trigger (GSWTRG)
  • 2 Global level software trigger (GLSWTRG)
  • 3 STRIG
  • 4 INT0 External interrupt
  • 5 TMR1 match
  • 6 TMR3 match
  • 7 TMR5 match
  • 8 OCMP1
  • 9 OCMP3
  • 10 OCMP5
  • 11 Comparator 1 (COUT)
  • 12 Comparator 2 (COUT)
  • 13 Reserved
  • 31 Reserved
TRGSRC84:0Trigger Source for Conversion of Analog Input AN8 Select bits
  • 0 No Trigger
  • 1 Global software edge Trigger (GSWTRG)
  • 2 Global level software trigger (GLSWTRG)
  • 3 STRIG
  • 4 INT0 External interrupt
  • 5 TMR1 match
  • 6 TMR3 match
  • 7 TMR5 match
  • 8 OCMP1
  • 9 OCMP3
  • 10 OCMP5
  • 11 Comparator 1 (COUT)
  • 12 Comparator 2 (COUT)
  • 13 Reserved
  • 31 Reserved

ADCCMPCON1ADC Digital Comparator 1 Control Register

Address
0xBF84B0A0
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
FieldBitsWhat it does
AINID13:8Digital Comparator 0 Analog Input Identification bits
  • 0 AN0 is being monitored
  • 1 AN1 is being monitored
  • 43 AN43 is being monitored
  • 44 AN44 is being monitored
  • 45 Reserved
  • 63 Reserved
ENDCMP7Digital Comparator 0 Enable bit
  • 0 Digital Comparator 0 is not enabled
  • 1 Digital Comparator 0 is enabled
DCMPGIEN6Digital Comparator 0 Global Interrupt Enable bit
  • 0 A Digital Comparator 0 interrupt is disabled
  • 1 A Digital Comparator 0 interrupt is generated when the DCMPED status bit (ADCCMP0CON) is set
DCMPED5Digital Comparator 0 Output True Event Status bit
  • 0 Digital Comparator 0 output is false (output of comparator is 0)
  • 1 Digital Comparator 0 output true event has occurred (output of Comparator is 1)
IEBTWN4Between Low/High Digital Comparator 0 Event bit
  • 0 Do not generate a digital comparator event
  • 1 Generate a digital comparator event when DCMPLO < DATA<31:0> < DCMPHI<15:0>
IEHIHI3High/High Digital Comparator 0 Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator 0 Event when DCMPHI < DATA<31:0>
IEHILO2High/Low Digital Comparator 0 Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator 0 Event when DATA < DCMPHI<15:0>
IELOHI1Low/High Digital Comparator 0 Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator 0 Event when DCMPLO < DATA<31:0>
IELOLO0Low/Low Digital Comparator 0 Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator 0 Event when DATA < DCMPLO<15:0>
CVDDATA31:16

ADCCMPCON2ADC Digital Comparator x Control Register (x = 2 through 6)

Address
0xBF84B0A4
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
AINID12:8Digital Comparator x Analog Input Identification bits
  • 0 AN0 is being monitored
  • 1 AN1 is being monitored
  • 30 AN30 is being monitored
  • 31 AN31 is being monitored
ENDCMP7Digital Comparator x Enable bit
  • 0 Digital Comparator x is not enabled
  • 1 Digital Comparator x is enabled
DCMPGIEN6Digital Comparator x Global Interrupt Enable bit
  • 0 A Digital Comparator x interrupt is disabled
  • 1 A Digital Comparator x interrupt is generated when the DCMPED status bit (ADCCMPxCON) is set
DCMPED5Digital Comparator x Output True Event Status bit
  • 0 Digital Comparator x output is false (output of Comparator is 0)
  • 1 Digital Comparator x output true event has occurred (output of Comparator is 1)
IEBTWN4Between Low/High Digital Comparator x Event bit
  • 0 Do not generate a digital comparator event
  • 1 Generate a digital comparator event when the DCMPLO < DATA<31:0> bits< DCMPHI<15:0> bits
IEHIHI3High/High Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DCMPHI < DATA<31:0> bits
IEHILO2High/Low Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DATA bits < DCMPHI<15:0> bits
IELOHI1Low/High Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DCMPLO < DATA<31:0> bits
IELOLO0Low/Low Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DATA bits < DCMPLO<15:0> bits

ADCCMPCON3ADC Digital Comparator x Control Register (x = 2 through 6)

Address
0xBF84B0A8
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
AINID12:8Digital Comparator x Analog Input Identification bits
  • 0 AN0 is being monitored
  • 1 AN1 is being monitored
  • 30 AN30 is being monitored
  • 31 AN31 is being monitored
ENDCMP7Digital Comparator x Enable bit
  • 0 Digital Comparator x is not enabled
  • 1 Digital Comparator x is enabled
DCMPGIEN6Digital Comparator x Global Interrupt Enable bit
  • 0 A Digital Comparator x interrupt is disabled
  • 1 A Digital Comparator x interrupt is generated when the DCMPED status bit (ADCCMPxCON) is set
DCMPED5Digital Comparator x Output True Event Status bit
  • 0 Digital Comparator x output is false (output of Comparator is 0)
  • 1 Digital Comparator x output true event has occurred (output of Comparator is 1)
IEBTWN4Between Low/High Digital Comparator x Event bit
  • 0 Do not generate a digital comparator event
  • 1 Generate a digital comparator event when the DCMPLO < DATA<31:0> bits< DCMPHI<15:0> bits
IEHIHI3High/High Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DCMPHI < DATA<31:0> bits
IEHILO2High/Low Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DATA bits < DCMPHI<15:0> bits
IELOHI1Low/High Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DCMPLO < DATA<31:0> bits
IELOLO0Low/Low Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DATA bits < DCMPLO<15:0> bits

ADCCMPCON4ADC Digital Comparator x Control Register (x = 2 through 6)

Address
0xBF84B0AC
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
AINID12:8Digital Comparator x Analog Input Identification bits
  • 0 AN0 is being monitored
  • 1 AN1 is being monitored
  • 30 AN30 is being monitored
  • 31 AN31 is being monitored
ENDCMP7Digital Comparator x Enable bit
  • 0 Digital Comparator x is not enabled
  • 1 Digital Comparator x is enabled
DCMPGIEN6Digital Comparator x Global Interrupt Enable bit
  • 0 A Digital Comparator x interrupt is disabled
  • 1 A Digital Comparator x interrupt is generated when the DCMPED status bit (ADCCMPxCON) is set
DCMPED5Digital Comparator x Output True Event Status bit
  • 0 Digital Comparator x output is false (output of Comparator is 0)
  • 1 Digital Comparator x output true event has occurred (output of Comparator is 1)
IEBTWN4Between Low/High Digital Comparator x Event bit
  • 0 Do not generate a digital comparator event
  • 1 Generate a digital comparator event when the DCMPLO < DATA<31:0> bits< DCMPHI<15:0> bits
IEHIHI3High/High Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DCMPHI < DATA<31:0> bits
IEHILO2High/Low Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DATA bits < DCMPHI<15:0> bits
IELOHI1Low/High Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DCMPLO < DATA<31:0> bits
IELOLO0Low/Low Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DATA bits < DCMPLO<15:0> bits

ADCCMPCON5ADC Digital Comparator x Control Register (x = 2 through 6)

Address
0xBF84B0B0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
AINID12:8Digital Comparator x Analog Input Identification bits
  • 0 AN0 is being monitored
  • 1 AN1 is being monitored
  • 30 AN30 is being monitored
  • 31 AN31 is being monitored
ENDCMP7Digital Comparator x Enable bit
  • 0 Digital Comparator x is not enabled
  • 1 Digital Comparator x is enabled
DCMPGIEN6Digital Comparator x Global Interrupt Enable bit
  • 0 A Digital Comparator x interrupt is disabled
  • 1 A Digital Comparator x interrupt is generated when the DCMPED status bit (ADCCMPxCON) is set
DCMPED5Digital Comparator x Output True Event Status bit
  • 0 Digital Comparator x output is false (output of Comparator is 0)
  • 1 Digital Comparator x output true event has occurred (output of Comparator is 1)
IEBTWN4Between Low/High Digital Comparator x Event bit
  • 0 Do not generate a digital comparator event
  • 1 Generate a digital comparator event when the DCMPLO < DATA<31:0> bits< DCMPHI<15:0> bits
IEHIHI3High/High Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DCMPHI < DATA<31:0> bits
IEHILO2High/Low Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DATA bits < DCMPHI<15:0> bits
IELOHI1Low/High Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DCMPLO < DATA<31:0> bits
IELOLO0Low/Low Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DATA bits < DCMPLO<15:0> bits

ADCCMPCON6ADC Digital Comparator x Control Register (x = 2 through 6)

Address
0xBF84B0B4
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
AINID12:8Digital Comparator x Analog Input Identification bits
  • 0 AN0 is being monitored
  • 1 AN1 is being monitored
  • 30 AN30 is being monitored
  • 31 AN31 is being monitored
ENDCMP7Digital Comparator x Enable bit
  • 0 Digital Comparator x is not enabled
  • 1 Digital Comparator x is enabled
DCMPGIEN6Digital Comparator x Global Interrupt Enable bit
  • 0 A Digital Comparator x interrupt is disabled
  • 1 A Digital Comparator x interrupt is generated when the DCMPED status bit (ADCCMPxCON) is set
DCMPED5Digital Comparator x Output True Event Status bit
  • 0 Digital Comparator x output is false (output of Comparator is 0)
  • 1 Digital Comparator x output true event has occurred (output of Comparator is 1)
IEBTWN4Between Low/High Digital Comparator x Event bit
  • 0 Do not generate a digital comparator event
  • 1 Generate a digital comparator event when the DCMPLO < DATA<31:0> bits< DCMPHI<15:0> bits
IEHIHI3High/High Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DCMPHI < DATA<31:0> bits
IEHILO2High/Low Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DATA bits < DCMPHI<15:0> bits
IELOHI1Low/High Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DCMPLO < DATA<31:0> bits
IELOLO0Low/Low Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DATA bits < DCMPLO<15:0> bits

ADCFSTATADC FIFO Status Register

Address
0xBF84B0B8
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
ADC4EN28ADC4 Enable bit
  • 0 Converted output data of ADC is not stored in the FIFO
  • 1 Converted output data of ADC is stored in the FIFO
ADC3EN27ADC3 Enable bit
  • 0 Converted output data of ADC is not stored in the FIFO
  • 1 Converted output data of ADC is stored in the FIFO
ADC2EN26ADC2 Enable bit
  • 0 Converted output data of ADC is not stored in the FIFO
  • 1 Converted output data of ADC is stored in the FIFO
ADC1EN25ADC1 Enable bit
  • 0 Converted output data of ADC is not stored in the FIFO
  • 1 Converted output data of ADC is stored in the FIFO
ADC0EN24ADC0 Enable bit
  • 0 Converted output data of ADC is not stored in the FIFO
  • 1 Converted output data of ADC is stored in the FIFO
FIEN23FIFO Interrupt Enable bit
  • 0 FIFO interrupts are disabled
  • 1 FIFO interrupts are enabled; an interrupt is generated once the FRDY bit is set
FRDY22FIFO Data Ready Interrupt Status bit
  • 0 No data is available in the FIFO
  • 1 FIFO has data to be read
FWROVERR21FIFO Write Overflow Error Status bit
  • 0 A write overflow error in the FIFO has not occurred
  • 1 A write overflow error in the FIFO has occurred (circular FIFO)
FCNT15:8
FSIGN7
ADCID2:0ADCx Identifier bits
  • 0 Converted data of ADC0 is stored in FIFO
  • 4 Converted data of ADC4 is stored in FIFO
  • 5 Reserved
  • 6 Reserved
  • 7 Reserved
FEN31FIFO Enable bit
  • 0 FIFO is disabled; no data is being saved into the FIFO
  • 1 FIFO is enabled

ADCFIFOADC FIFO Data Register

Address
0xBF84B0BC
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCBASEADC Base Register

Address
0xBF84B0C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADCBASE15:0

ADCTRGSNSADC Trigger Level/Edge Sensitivity Register

Address
0xBF84B0D0
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
LVL1111Trigger Level and Edge Sensitivity bit 11
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL1010Trigger Level and Edge Sensitivity bit 10
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL99Trigger Level and Edge Sensitivity bit 9
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL88Trigger Level and Edge Sensitivity bit 8
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL77Trigger Level and Edge Sensitivity bit 7
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL66Trigger Level and Edge Sensitivity bit 6
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL55Trigger Level and Edge Sensitivity bit 5
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL44Trigger Level and Edge Sensitivity bit 4
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL33Trigger Level and Edge Sensitivity bit 3
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL22Trigger Level and Edge Sensitivity bit 2
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL11Trigger Level and Edge Sensitivity bit 1
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL00Trigger Level and Edge Sensitivity bit 0
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)

ADC0TIMEDedicated ADCx Timing Register x (x = 0 through 4)

Address
0xBF84B0D4
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ADCEIS28:26ADCx Early Interrupt Select bits
  • 0 The data ready interrupt is generated 1 ADC clock prior to the end of conversion
  • 1 The data ready interrupt is generated 2 ADC clocks prior to the end of conversion
  • 2 The data ready interrupt is generated 3 ADC clocks prior to the end of conversion
  • 3 The data ready interrupt is generated 4 ADC clocks prior to the end of conversion
  • 4 The data ready interrupt is generated 5 ADC clocks prior to the end of conversion
  • 5 The data ready interrupt is generated 6 ADC clocks prior to the end of conversion
  • 6 The data ready interrupt is generated 7 ADC clocks prior to the end of conversion
  • 7 The data ready interrupt is generated 8 ADC clocks prior to the end of conversion
SELRES25:24ADCx Resolution Select bits
  • 0 6 bits
  • 1 8 bits
  • 2 10 bits
  • 3 12 bits
ADCDIV22:16ADCx Clock Divisor bits
  • 0 Reserved
  • 1 2 * Tq = Tadx
  • 2 4 * Tq = Tadx
  • 3 6 * Tq = Tadx
  • 127 254 * Tq = Tadx
SAMC9:0ADCx Sample Time bits
  • 0 2 Tadx
  • 1 3 Tadx
  • 1023 1025 Tadx

ADC1TIMEDedicated ADCx Timing Register x (x = 0 through 4)

Address
0xBF84B0D8
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ADCEIS28:26ADCx Early Interrupt Select bits
  • 0 The data ready interrupt is generated 1 ADC clock prior to the end of conversion
  • 1 The data ready interrupt is generated 2 ADC clocks prior to the end of conversion
  • 2 The data ready interrupt is generated 3 ADC clocks prior to the end of conversion
  • 3 The data ready interrupt is generated 4 ADC clocks prior to the end of conversion
  • 4 The data ready interrupt is generated 5 ADC clocks prior to the end of conversion
  • 5 The data ready interrupt is generated 6 ADC clocks prior to the end of conversion
  • 6 The data ready interrupt is generated 7 ADC clocks prior to the end of conversion
  • 7 The data ready interrupt is generated 8 ADC clocks prior to the end of conversion
SELRES25:24ADCx Resolution Select bits
  • 0 6 bits
  • 1 8 bits
  • 2 10 bits
  • 3 12 bits
ADCDIV22:16ADCx Clock Divisor bits
  • 0 Reserved
  • 1 2 * Tq = Tadx
  • 2 4 * Tq = Tadx
  • 3 6 * Tq = Tadx
  • 127 254 * Tq = Tadx
SAMC9:0ADCx Sample Time bits
  • 0 2 Tadx
  • 1 3 Tadx
  • 1023 1025 Tadx

ADC2TIMEDedicated ADCx Timing Register x (x = 0 through 4)

Address
0xBF84B0DC
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ADCEIS28:26ADCx Early Interrupt Select bits
  • 0 The data ready interrupt is generated 1 ADC clock prior to the end of conversion
  • 1 The data ready interrupt is generated 2 ADC clocks prior to the end of conversion
  • 2 The data ready interrupt is generated 3 ADC clocks prior to the end of conversion
  • 3 The data ready interrupt is generated 4 ADC clocks prior to the end of conversion
  • 4 The data ready interrupt is generated 5 ADC clocks prior to the end of conversion
  • 5 The data ready interrupt is generated 6 ADC clocks prior to the end of conversion
  • 6 The data ready interrupt is generated 7 ADC clocks prior to the end of conversion
  • 7 The data ready interrupt is generated 8 ADC clocks prior to the end of conversion
SELRES25:24ADCx Resolution Select bits
  • 0 6 bits
  • 1 8 bits
  • 2 10 bits
  • 3 12 bits
ADCDIV22:16ADCx Clock Divisor bits
  • 0 Reserved
  • 1 2 * Tq = Tadx
  • 2 4 * Tq = Tadx
  • 3 6 * Tq = Tadx
  • 127 254 * Tq = Tadx
SAMC9:0ADCx Sample Time bits
  • 0 2 Tadx
  • 1 3 Tadx
  • 1023 1025 Tadx

ADC3TIMEDedicated ADCx Timing Register x (x = 0 through 4)

Address
0xBF84B0E0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ADCEIS28:26ADCx Early Interrupt Select bits
  • 0 The data ready interrupt is generated 1 ADC clock prior to the end of conversion
  • 1 The data ready interrupt is generated 2 ADC clocks prior to the end of conversion
  • 2 The data ready interrupt is generated 3 ADC clocks prior to the end of conversion
  • 3 The data ready interrupt is generated 4 ADC clocks prior to the end of conversion
  • 4 The data ready interrupt is generated 5 ADC clocks prior to the end of conversion
  • 5 The data ready interrupt is generated 6 ADC clocks prior to the end of conversion
  • 6 The data ready interrupt is generated 7 ADC clocks prior to the end of conversion
  • 7 The data ready interrupt is generated 8 ADC clocks prior to the end of conversion
SELRES25:24ADCx Resolution Select bits
  • 0 6 bits
  • 1 8 bits
  • 2 10 bits
  • 3 12 bits
ADCDIV22:16ADCx Clock Divisor bits
  • 0 Reserved
  • 1 2 * Tq = Tadx
  • 2 4 * Tq = Tadx
  • 3 6 * Tq = Tadx
  • 127 254 * Tq = Tadx
SAMC9:0ADCx Sample Time bits
  • 0 2 Tadx
  • 1 3 Tadx
  • 1023 1025 Tadx

ADC4TIMEDedicated ADCx Timing Register x (x = 0 through 4)

Address
0xBF84B0E4
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ADCEIS28:26ADCx Early Interrupt Select bits
  • 0 The data ready interrupt is generated 1 ADC clock prior to the end of conversion
  • 1 The data ready interrupt is generated 2 ADC clocks prior to the end of conversion
  • 2 The data ready interrupt is generated 3 ADC clocks prior to the end of conversion
  • 3 The data ready interrupt is generated 4 ADC clocks prior to the end of conversion
  • 4 The data ready interrupt is generated 5 ADC clocks prior to the end of conversion
  • 5 The data ready interrupt is generated 6 ADC clocks prior to the end of conversion
  • 6 The data ready interrupt is generated 7 ADC clocks prior to the end of conversion
  • 7 The data ready interrupt is generated 8 ADC clocks prior to the end of conversion
SELRES25:24ADCx Resolution Select bits
  • 0 6 bits
  • 1 8 bits
  • 2 10 bits
  • 3 12 bits
ADCDIV22:16ADCx Clock Divisor bits
  • 0 Reserved
  • 1 2 * Tq = Tadx
  • 2 4 * Tq = Tadx
  • 3 6 * Tq = Tadx
  • 127 254 * Tq = Tadx
SAMC9:0ADCx Sample Time bits
  • 0 2 Tadx
  • 1 3 Tadx
  • 1023 1025 Tadx

ADCEIQEN1

Address
0xBF84B0F0
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
EIEN1818
EIEN1717
EIEN1616
EIEN1515
EIEN1414
EIEN1313
EIEN1212
EIEN1111
EIEN1010
EIEN99
EIEN88
EIEN77
EIEN66
EIEN55
EIEN44
EIEN33
EIEN22
EIEN11
EIEN00

ADCEIQEN2

Address
0xBF84B0F4
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
EIEN4412
EIEN4311

ADCEISTAT1ADC Early Interrupt Status Register 1

Address
0xBF84B0F8
Reset
0x00000000
Access
read only
Size
32-bit
19 fields
FieldBitsWhat it does
EIRDY1818Early Interrupt for Corresponding Analog Input Ready bit 18
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs
EIRDY1717Early Interrupt for Corresponding Analog Input Ready bit 17
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs
EIRDY1616Early Interrupt for Corresponding Analog Input Ready bit 16
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs
EIRDY1515Early Interrupt for Corresponding Analog Input Ready bit 15
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs
EIRDY1414Early Interrupt for Corresponding Analog Input Ready bit 14
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs
EIRDY1313Early Interrupt for Corresponding Analog Input Ready bit 13
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs
EIRDY1212Early Interrupt for Corresponding Analog Input Ready bit 12
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs
EIRDY1111Early Interrupt for Corresponding Analog Input Ready bit 11
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs
EIRDY1010Early Interrupt for Corresponding Analog Input Ready bit 10
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs
EIRDY99Early Interrupt for Corresponding Analog Input Ready bit 9
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs
EIRDY88Early Interrupt for Corresponding Analog Input Ready bit 8
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs
EIRDY77Early Interrupt for Corresponding Analog Input Ready bit 7
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs
EIRDY66Early Interrupt for Corresponding Analog Input Ready bit 6
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs
EIRDY55Early Interrupt for Corresponding Analog Input Ready bit 5
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs
EIRDY44Early Interrupt for Corresponding Analog Input Ready bit 4
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs
EIRDY33Early Interrupt for Corresponding Analog Input Ready bit 3
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs
EIRDY22Early Interrupt for Corresponding Analog Input Ready bit 2
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs
EIRDY11Early Interrupt for Corresponding Analog Input Ready bit 1
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs
EIRDY00Early Interrupt for Corresponding Analog Input Ready bit 0
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs

ADCEISTAT2ADC Early Interrupt Status Register 2

Address
0xBF84B0FC
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
EIRDY4412Early Interrupt for Corresponding Analog Input Ready bit 44
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN2 register. For the Class 1 analog inputs
EIRDY4311Early Interrupt for Corresponding Analog Input Ready bit 43
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN2 register. For the Class 1 analog inputs

ADCANCONADC Analog Warm-up Control Register

Address
0xBF84B100
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
WKUPCLKCNT27:24Wake-up Clock Count bits
  • 0 16 clocks
  • 1 16 clocks
  • 2 16 clocks
  • 3 16 clocks
  • 4 16 clocks
  • 5 32 clocks
  • 6 64 clocks
  • 15 32
WKIEN723Shared ADC Wake-up Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt and generate interrupt when the WKRDY7 status bit is set
WKIEN420ADC 4 Wake-up Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt and generate interrupt when the WKRDYx status bit is set
WKIEN319ADC 3 Wake-up Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt and generate interrupt when the WKRDYx status bit is set
WKIEN218ADC 2 Wake-up Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt and generate interrupt when the WKRDYx status bit is set
WKIEN117ADC 1 Wake-up Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt and generate interrupt when the WKRDYx status bit is set
WKIEN016ADC 0 Wake-up Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt and generate interrupt when the WKRDYx status bit is set
WKRDY715Shared ADC Wake-up Status bit
  • 0 ADC7 Analog and Bias circuitry is not ready
  • 1 ADC7 Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting ANEN7 to 1
WKRDY412ADC 4 Wake-up Status bit
  • 0 ADCx Analog and Bias circuitry is not ready
  • 1 ADCx Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting ANENx to 1
WKRDY311ADC 3 Wake-up Status bit
  • 0 ADCx Analog and Bias circuitry is not ready
  • 1 ADCx Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting ANENx to 1
WKRDY210ADC 2 Wake-up Status bit
  • 0 ADCx Analog and Bias circuitry is not ready
  • 1 ADCx Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting ANENx to 1
WKRDY19ADC 1 Wake-up Status bit
  • 0 ADCx Analog and Bias circuitry is not ready
  • 1 ADCx Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting ANENx to 1
WKRDY08ADC 0 Wake-up Status bit
  • 0 ADCx Analog and Bias circuitry is not ready
  • 1 ADCx Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting ANENx to 1
ANEN77Shared ADC Analog and Bias Circuitry Enable bit
  • 0 Analog and bias circuitry disabled
  • 1 Analog and bias circuitry enabled. Once the analog and bias circuit is enabled
ANEN44ADC4 Analog and Bias Circuitry Enable bit
  • 0 Analog and bias circuitry disabled
  • 1 Analog and bias circuitry enabled. Once the analog and bias circuit is enabled
ANEN33ADC3 Analog and Bias Circuitry Enable bit
  • 0 Analog and bias circuitry disabled
  • 1 Analog and bias circuitry enabled. Once the analog and bias circuit is enabled
ANEN22ADC2 Analog and Bias Circuitry Enable bit
  • 0 Analog and bias circuitry disabled
  • 1 Analog and bias circuitry enabled. Once the analog and bias circuit is enabled
ANEN11ADC1 Analog and Bias Circuitry Enable bit
  • 0 Analog and bias circuitry disabled
  • 1 Analog and bias circuitry enabled. Once the analog and bias circuit is enabled
ANEN00ADC0 Analog and Bias Circuitry Enable bit
  • 0 Analog and bias circuitry disabled
  • 1 Analog and bias circuitry enabled. Once the analog and bias circuit is enabled

ADC0CFGADC0 Configuration Register

Address
0xBF84B180
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADCCFG31:0

ADC1CFGADC1 Configuration Register

Address
0xBF84B184
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADCCFG31:0

ADC2CFGADC2 Configuration Register

Address
0xBF84B188
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADCCFG31:0

ADC3CFGADC3 Configuration Register

Address
0xBF84B18C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADCCFG31:0

ADC4CFGADC4 Configuration Register

Address
0xBF84B190
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADCCFG31:0

ADC7CFGADC7 Configuration Register

Address
0xBF84B19C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADCCFG31:0

ADCSYSCFG0

Address
0xBF84B1C0
Reset
0x00000000
Access
read only
Size
32-bit
32 fields
FieldBitsWhat it does
AN3030
AN2929
AN2828
AN2727
AN2626
AN2525
AN2424
AN2323
AN2222
AN2121
AN2020
AN1919
AN1818
AN1717
AN1616
AN1515
AN1414
AN1313
AN1212
AN1111
AN1010
AN99
AN88
AN77
AN66
AN55
AN44
AN33
AN22
AN11
AN00
AN3131

ADCSYSCFG1ADC System Configuration Register 1

Address
0xBF84B1C4
Reset
0x00000000
Access
read only
Size
32-bit
32 fields
FieldBitsWhat it does
AN6230
AN6129
AN6028
AN5927
AN5826
AN5725
AN5624
AN5523
AN5422
AN5321
AN5220
AN5119
AN5018
AN4917
AN4816
AN4715
AN4614
AN4513
AN4412
AN4311
AN4210
AN419
AN408
AN397
AN386
AN375
AN364
AN353
AN342
AN331
AN320
AN6331

ADCDATA0ADC0 Output Data Register

Address
0xBF84B200
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA1ADC1 Output Data Register

Address
0xBF84B204
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA2ADC2 Output Data Register

Address
0xBF84B208
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA3ADC3 Output Data Register

Address
0xBF84B20C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA4ADC4 Output Data Register

Address
0xBF84B210
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA5ADC5 Output Data Register

Address
0xBF84B214
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA6ADC6 Output Data Register

Address
0xBF84B218
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA7ADC7 Output Data Register

Address
0xBF84B21C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA8ADC8 Output Data Register

Address
0xBF84B220
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA9ADC9 Output Data Register

Address
0xBF84B224
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA10ADC10 Output Data Register

Address
0xBF84B228
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA11ADC11 Output Data Register

Address
0xBF84B22C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA12ADC12 Output Data Register

Address
0xBF84B230
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA13ADC13 Output Data Register

Address
0xBF84B234
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA14ADC14 Output Data Register

Address
0xBF84B238
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA15ADC15 Output Data Register

Address
0xBF84B23C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA16ADC16 Output Data Register

Address
0xBF84B240
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA17ADC17 Output Data Register

Address
0xBF84B244
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA18ADC18 Output Data Register

Address
0xBF84B248
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA43ADC43 Output Data Register

Address
0xBF84B2AC
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA44ADC44 Output Data Register

Address
0xBF84B2B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0