The 6 registers of DMAC (DMA controller), from 0xBF811000, with their reset value and every field. The PIC32MZ1024EFE144 has 1315 registers in 91 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
DMAC DMA controller
DMACONDMA Controller Control Register
Address
0xBF811000
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
ON
15
DMA On bit
0 DMA module is enabled
0 DMA module is disabled
SUSPEND
12
DMA Suspend bit
0 DMA operates normally
1 DMA transfers are suspended to allow CPU uninterrupted access to data bus
DMABUSY
11
DMA Module Busy bit
0 DMA module is disabled and not actively transferring data
1 DMA module is active and is transferring data
DMASTATDMA Status Register
Address
0xBF811010
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
DMACH
2:0
RDWR
31
Read/Write Status bit
0 Last DMA bus access when an error was detected was a write
1 Last DMA bus access when an error was detected was a read
DMAADDRDMA Address Register
Address
0xBF811020
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
DMAADDR
31:0
DCRCCONDMA CRC Control Register
Address
0xBF811030
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
BYTO
29:28
CRC Byte Order Selection bits
0 No swapping (i.e.
1 Endian byte swap on word boundaries (i.e.
2 Swap half-words on word boundaries (i.e.
3 Endian byte swap on half-word boundaries (i.e.
WBO
27
CRC Write Byte Order Selection bit
0 Source data is written to the destination unaltered
1 Source data is written to the destination re-ordered as defined by BYTO
BITO
24
CRC Bit Order Selection bit
0 (When CRCTYP (i.e.
1 (When CRCTYP (ie
PLEN
12:8
Polynomial Length bits
CRCEN
7
CRC Enable bit
0 CRC module is disabled and channel transfers proceed normally
1 CRC module is enabled and channel transfers are routed through the CRC module
CRCAPP
6
CRC Append Mode bit
0 The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the destination
1 The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer completes the DMA writes the calculated CRC value to the location given by CHxDSA
CRCTYP
5
CRC Type Selection bit
0 The CRC module will calculate a LFSR CRC
1 The CRC module will calculate an IP header checksum
BETA