The 4 registers of CFG (Configuration and pin control), from 0xBF800000, with their reset value and every field. The PIC32MZ1024EFF064 has 1507 registers in 85 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
CFG Configuration and pin control
CFGCONConfiguration Control Register
Address
0xBF800000
Reset
0x00000000
Access
read/write
Size
32-bit
13 fields
Field
Bits
What it does
DMAPRI
25
DMA Read and DMA Write Arbitration Priority to SRAM bit(1)
0 DMA uses Least Recently Serviced Arbitration (same as other initiators)
1 DMA gets High Priority access to SRAM
EXLPRI
24
ICACLK
17
Input Capture Alternate Clock Selection bit(1)
0 All Input Capture modules use Timer2/3 as their timebase clock
1 Input Capture modules use an alternative Timer pair as their timebase clock
OCACLK
16
Output Compare Alternate Clock Selection bit(1)
0 All Output Compare modules use Timer2/3 as their timebase clock
1 Output Compare modules use an alternative Timer pair as their timebase clock
IOLOCK
13
Peripheral Pin Select Lock bit(1)
0 Peripheral Pin Select is not locked. Writes to PPS registers are allowed
1 Peripheral Pin Select is locked. Writes to PPS registers are not allowed
PMDLOCK
12
Peripheral Module Disable bit(1)
0 Peripheral module is not locked. Writes to PMD registers are allowed
1 Peripheral module is locked. Writes to PMD registers are not allowed
PGLOCK
11
Permission Group Lock bit(1)
0 Permission Group registers are not locked. Writes to PG registers are allowed
1 Permission Group registers are locked. Writes to PG registers are not allowed
USBSSEN
8
USB Suspend Sleep Enable bit(1)
0 USB PHY clock continues to run when Sleep is active
1 USB PHY clock is shut down when Sleep mode is active
IOANCPN
7
ECCCON
5:4
Flash ECC Configuration bits
0 Flash ECC is enabled (ECCCON bits are locked; disables word Flash writes)
1 Dynamic Flash ECC is enabled (ECCCON bits are locked)
2 ECC and dynamic ECC are disabled (ECCCON bits are locked)
3 ECC and dynamic ECC are disabled (ECCCON bits are writable)
JTAGEN
3
JTAG Port Enable bit
0 Disable the JTAG port
1 Enable the JTAG port
TROEN
2
Trace Output Enable bit
0 Disable trace outputs and stop trace clock
1 Enable trace outputs and start trace clock (trace probe must be present)
BETA