The 12 registers of DCH0 (DMA channel 0), from 0xBF811060, with their reset value and every field. The PIC32MZ1024EFF124 has 1664 registers in 92 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
DCH0 DMA channel 0
DCH0CONDMA Channel x Control Register
Address
0xBF811060
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
CHBUSY
15
Channel Busy bit
0 Channel is inactive or has been disabled
1 Channel is active or has been enabled
CHPIGNEN
13
Enable Pattern Ignore Byte bit
0 Disable this feature
1 Treat any byte that matches the CHPIGN bits as a dont care when pattern matching is enabled
CHPATLEN
11
Pattern Length bit
0 1 byte length
1 2 byte length
CHCHNS
8
Chain Channel Selection bit
0 Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
1 Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
CHEN
7
Channel Enable bit
0 Channel is disabled
1 Channel is enabled
CHAED
6
Channel Allow Events If Disabled bit
0 Channel start/abort events will be ignored if the channel is disabled
1 Channel start/abort events will be registered
CHCHN
5
Channel Chain Enable bit
0 Do not allow channel to be chained
1 Allow channel to be chained
CHAEN
4
Channel Automatic Enable bit
0 Channel is disabled on block transfer complete
1 Channel is continuously enabled
CHEDET
2
Channel Event Detected bit
0 No events have been detected
1 An event has been detected
CHPRI
1:0
Channel Priority bits
0 Channel has priority 0
1 Channel has priority 1
2 Channel has priority 2
3 Channel has priority 3 (highest)
CHPIGN
31:24
DCH0ECONDMA Channel x Event Control Register
Address
0xBF811070
Reset
0x00FFFF00
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
CHAIRQ
23:16
Channel Transfer Abort IRQ bits
0 Interrupt 0 will abort any transfers in progress and set CHAIF flag
1 Interrupt 1 will abort any transfers in progress and set CHAIF flag
255 Interrupt 255 will abort any transfers in progress and set CHAIF flag
CHSIRQ
15:8
Channel Transfer Start IRQ bits
0 Interrupt 0 will initiate a DMA transfer
1 Interrupt 1 will initiate a DMA transfer
255 Interrupt 255 will initiate a DMA transfer
CFORCE
7
DMA Forced Transfer bit
0 This bit always reads 0
1 A DMA transfer is forced to begin when this bit is written to a 1
CABORT
6
DMA Abort Transfer bit
0 This bit always reads 0
1 A DMA transfer is aborted when this bit is written to a 1
PATEN
5
Channel Pattern Match Abort Enable bit
0 Pattern match is disabled
1 Abort transfer and clear CHEN on pattern match
SIRQEN
4
Channel Start IRQ Enable bit
0 Interrupt number CHSIRQ is ignored and does not start a transfer
1 Start channel cell transfer if an interrupt matching CHSIRQ occurs
AIRQEN
3
Channel Abort IRQ Enable bit
0 Interrupt number CHAIRQ is ignored and does not terminate a transfer
1 Channel transfer is aborted if an interrupt matching CHAIRQ occurs
DCH0INTDMA Channel x Interrupt Control Register
Address
0xBF811080
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
CHSDIE
23
Channel Source Done Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHSHIE
22
Channel Source Half Empty Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHDDIE
21
Channel Destination Done Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHDHIE
20
Channel Destination Half Full Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHBCIE
19
Channel Block Transfer Complete Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHCCIE
18
Channel Cell Transfer Complete Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHTAIE
17
Channel Transfer Abort Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHERIE
16
Channel Address Error Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CHSDIF
7
Channel Source Done Interrupt Flag bit
0 No interrupt is pending
1 Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
CHSHIF
6
Channel Source Half Empty Interrupt Flag bit
0 No interrupt is pending
1 Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
CHDDIF
5
Channel Destination Done Interrupt Flag bit
0 No interrupt is pending
1 Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
CHDHIF
4
Channel Destination Half Full Interrupt Flag bit
0 No interrupt is pending
1 Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
CHBCIF
3
Channel Block Transfer Complete Interrupt Flag bit
0 No interrupt is pending
1 A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred)
CHCCIF
2
Channel Cell Transfer Complete Interrupt Flag bit
0 No interrupt is pending
1 A cell transfer has been completed (CHCSIZ bytes have been transferred)
CHTAIF
1
Channel Transfer Abort Interrupt Flag bit
0 No interrupt is pending
1 An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
CHERIF
0
Channel Address Error Interrupt Flag bit
0 No interrupt is pending
1 A channel address error has been detected Either the source or the destination address is invalid.
DCH0SSADMA Channel x Source Start Address Register
Address
0xBF811090
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CHSSA
31:0
DCH0DSADMA Channel x Destination Start Address Register
Address
0xBF8110A0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CHDSA
31:0
DCH0SSIZDMA Channel x Source Size Register
Address
0xBF8110B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CHSSIZ
15:0
Channel Source Size bits
0 65536 byte source size
1 1 byte source size
2 2 byte source size
DCH0DSIZDMA Channel x Destination Size Register
Address
0xBF8110C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CHDSIZ
15:0
Channel Destination Size bits
0 65536 byte destination size
1 1 byte destination size
2 2 byte destination size
DCH0SPTRDMA Channel x Source Pointer Register
Address
0xBF8110D0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CHSPTR
15:0
Channel Source Pointer bits
0 Points to byte 0 of the source
1 Points to byte 1 of the source
65535 Points to byte 65535 of the source
DCH0DPTRDMA Channel x Destination Pointer Register
Address
0xBF8110E0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CHDPTR
15:0
Channel Destination Pointer bits
0 Points to byte 0 of the destination
1 Points to byte 1 of the destination
65535 Points to byte 65535 of the destination
DCH0CSIZDMA Channel x Cell-Size Register
Address
0xBF8110F0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CHCSIZ
15:0
Channel Cell-Size bits
0 65536 bytes transferred on an event
1 1 byte transferred on an event
2 2 bytes transferred on an event
65535 65535 bytes transferred on an event
DCH0CPTRDMA Channel x Cell Pointer Register
Address
0xBF811100
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CHCPTR
15:0
Channel Cell Progress Pointer bits
0 0 bytes have been transferred since the last event
1 1 byte has been transferred since the last event
65535 65535 bytes have been transferred since the last event
BETA