PIC32MZ1024EFF124 OSC registers

The 12 registers of OSC (Oscillator and clocks), from 0xBF801200, with their reset value and every field. The PIC32MZ1024EFF124 has 1664 registers in 92 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

OSC Oscillator and clocks

OSCCONOscillator Control Register

Address
0xBF801200
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
FieldBitsWhat it does
FRCDIV26:24Internal Fast RC Oscillator Clock Divider bits
  • 0 FRC divided by 1 (default setting)
  • 1 FRC divided by 2
  • 2 FRC divided by 4
  • 3 FRC divided by 8
  • 4 FRC divided by 16
  • 5 FRC divided by 32
  • 6 FRC divided by 64
  • 7 FRC divided by 256
DRMEN23Dream Mode Enable bit
  • 0 Dream mode is disabled
  • 1 Dream mode is enabled
SLP2SPD21Sleep 2-speed Startup Control bit
  • 0 Use the selected clock directly
  • 1 Use FRC as SYSCLK until selected clock is ready
COSC14:12Current Oscillator Selection bits
  • 0 Internal Fast RC (FRC) Oscillator divided by FRCDIV bits (FRCDIV)
  • 1 System PLL (SPLL)
  • 2 Primary Oscillator (Posc) (HS or EC)
  • 3 Reserved
  • 4 Secondary Oscillator (Sosc)
  • 5 Internal Low-Power RC (LPRC) Oscillator
  • 6 Back-up Fast RC (BFRC) Oscillator
  • 7 Internal Fast RC (FRC) Oscillator divided by FRCDIV bits (FRCDIV)
NOSC10:8New Oscillator Selection bits
  • 0 Internal Fast RC (FRC) Oscillator divided by FRCDIV bits (FRCDIV)
  • 1 System PLL (SPLL)
  • 2 Primary Oscillator (Posc) (HS or EC)
  • 3 Reserved
  • 4 Secondary Oscillator (Sosc)
  • 5 Internal Low-Power RC (LPRC) Oscillator
  • 6 Reserved
  • 7 Internal Fast RC (FRC) Oscillator divided by FRCDIV bits (FRCDIV)
CLKLOCK7Clock Selection Lock Enable bit
  • 0 Clock and PLL selections are not locked and may be modified
  • 1 Clock and PLL selections are locked
SLPEN4Sleep Mode Enable bit
  • 0 Device will enter Idle mode when a WAIT instruction is executed
  • 1 Device will enter Sleep mode when a WAIT instruction is executed
CF3Clock Fail Detect bit
  • 0 No clock failure has been detected
  • 1 FSCM has detected a clock failure
SOSCEN1Secondary Oscillator Enable bit
  • 0 Disable Secondary Oscillator
  • 1 Enable Secondary Oscillator
OSWEN0Oscillator Switch Enable bit
  • 0 Oscillator switch is complete
  • 1 Initiate an oscillator switch to selection specified by NOSC bits

OSCTUNFRC Tuning Register

Address
0xBF801210
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TUN5:0FRC Oscillator Tuning bits
  • 0 Center frequency; Oscillator runs at nominal frequency (8 MHz)
  • 31 Center frequency +2%
  • 32 Center frequency -2%

SPLLCONSystem PLL Control Register

Address
0xBF801220
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
PLLODIV26:24System PLL Output Clock Divider bits
  • 0 Reserved
  • 1 PLL Divide by 2
  • 2 PLL Divide by 4
  • 3 PLL Divide by 8
  • 4 PLL Divide by 16
  • 5 PLL Divide by 32
  • 6 Reserved
  • 7 Reserved
PLLMULT22:16System PLL Multiplier bits
  • 0 Multiply by 1
  • 1 Multiply by 2
  • 124 Multiply by 125
  • 125 Multiply by 126
  • 126 Multiply by 127
  • 127 Multiply by 128
PLLIDIV10:8System PLL Input Clock Divider bits
  • 0 Divide by 1
  • 1 Divide by 2
  • 2 Divide by 3
  • 3 Divide by 4
  • 4 Divide by 5
  • 5 Divide by 6
  • 6 Divide by 7
  • 7 Divide by 8
PLLICLK7System PLL Input Clock Source bit
  • 0 Posc is selected as the input to the System PLL
  • 1 FRC is selected as the input to the System PLL
PLLRANGE2:0System PLL Frequency Range Selection bits
  • 0 Bypass
  • 1 5-10 MHz
  • 2 8-16 MHz
  • 3 13-26 MHz
  • 4 21-42 MHz
  • 5 34-64 MHz
  • 6 Reserved
  • 7 Reserved

PB1DIVPeripheral Bus x Clock Divisor Control Register (x = 1-7)

Address
0xBF801300
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
PBDIVRDY11Peripheral Bus x Clock Divisor Ready bit
  • 0 Clock divisor logic is currently switching values and the PBxDIV bits cannot be written
  • 1 Clock divisor logic is not switching divisors and the PBxDIV bits may be written
PBDIV6:0Peripheral Bus x Clock Divisor Control bits
  • 0 PBCLKx is SYSCLK divided by 1 (default value for x = 7)
  • 1 PBCLKx is SYSCLK divided by 2 (default value for x 7)
  • 2 PBCLKx is SYSCLK divided by 3
  • 3 PBCLKx is SYSCLK divided by 4
  • 126 PBCLKx is SYSCLK divided by 127
  • 127 PBCLKx is SYSCLK divided by 128

PB2DIVPeripheral Bus x Clock Divisor Control Register (x = 1-7)

Address
0xBF801310
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
ON15Peripheral Bus x Output Clock Enable bit
  • 0 Output clock is disabled
  • 1 Output clock is enabled
PBDIVRDY11Peripheral Bus x Clock Divisor Ready bit
  • 0 Clock divisor logic is currently switching values and the PBxDIV bits cannot be written
  • 1 Clock divisor logic is not switching divisors and the PBxDIV bits may be written
PBDIV6:0Peripheral Bus x Clock Divisor Control bits
  • 0 PBCLKx is SYSCLK divided by 1 (default value for x = 7)
  • 1 PBCLKx is SYSCLK divided by 2 (default value for x 7)
  • 2 PBCLKx is SYSCLK divided by 3
  • 3 PBCLKx is SYSCLK divided by 4
  • 126 PBCLKx is SYSCLK divided by 127
  • 127 PBCLKx is SYSCLK divided by 128

PB3DIVPeripheral Bus x Clock Divisor Control Register (x = 1-7)

Address
0xBF801320
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
ON15Peripheral Bus x Output Clock Enable bit
  • 0 Output clock is disabled
  • 1 Output clock is enabled
PBDIVRDY11Peripheral Bus x Clock Divisor Ready bit
  • 0 Clock divisor logic is currently switching values and the PBxDIV bits cannot be written
  • 1 Clock divisor logic is not switching divisors and the PBxDIV bits may be written
PBDIV6:0Peripheral Bus x Clock Divisor Control bits
  • 0 PBCLKx is SYSCLK divided by 1 (default value for x = 7)
  • 1 PBCLKx is SYSCLK divided by 2 (default value for x 7)
  • 2 PBCLKx is SYSCLK divided by 3
  • 3 PBCLKx is SYSCLK divided by 4
  • 126 PBCLKx is SYSCLK divided by 127
  • 127 PBCLKx is SYSCLK divided by 128

PB4DIVPeripheral Bus x Clock Divisor Control Register (x = 1-7)

Address
0xBF801330
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
ON15Peripheral Bus x Output Clock Enable bit
  • 0 Output clock is disabled
  • 1 Output clock is enabled
PBDIVRDY11Peripheral Bus x Clock Divisor Ready bit
  • 0 Clock divisor logic is currently switching values and the PBxDIV bits cannot be written
  • 1 Clock divisor logic is not switching divisors and the PBxDIV bits may be written
PBDIV6:0Peripheral Bus x Clock Divisor Control bits
  • 0 PBCLKx is SYSCLK divided by 1 (default value for x = 7)
  • 1 PBCLKx is SYSCLK divided by 2 (default value for x 7)
  • 2 PBCLKx is SYSCLK divided by 3
  • 3 PBCLKx is SYSCLK divided by 4
  • 126 PBCLKx is SYSCLK divided by 127
  • 127 PBCLKx is SYSCLK divided by 128

PB5DIVPeripheral Bus x Clock Divisor Control Register (x = 1-7)

Address
0xBF801340
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
ON15Peripheral Bus x Output Clock Enable bit
  • 0 Output clock is disabled
  • 1 Output clock is enabled
PBDIVRDY11Peripheral Bus x Clock Divisor Ready bit
  • 0 Clock divisor logic is currently switching values and the PBxDIV bits cannot be written
  • 1 Clock divisor logic is not switching divisors and the PBxDIV bits may be written
PBDIV6:0Peripheral Bus x Clock Divisor Control bits
  • 0 PBCLKx is SYSCLK divided by 1 (default value for x = 7)
  • 1 PBCLKx is SYSCLK divided by 2 (default value for x 7)
  • 2 PBCLKx is SYSCLK divided by 3
  • 3 PBCLKx is SYSCLK divided by 4
  • 126 PBCLKx is SYSCLK divided by 127
  • 127 PBCLKx is SYSCLK divided by 128

PB7DIVPeripheral Bus x Clock Divisor Control Register (x = 1-7)

Address
0xBF801360
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
ON15Peripheral Bus x Output Clock Enable bit
  • 0 Output clock is disabled
  • 1 Output clock is enabled
PBDIVRDY11Peripheral Bus x Clock Divisor Ready bit
  • 0 Clock divisor logic is currently switching values and the PBxDIV bits cannot be written
  • 1 Clock divisor logic is not switching divisors and the PBxDIV bits may be written
PBDIV6:0Peripheral Bus x Clock Divisor Control bits
  • 0 PBCLKx is SYSCLK divided by 1 (default value for x = 7)
  • 1 PBCLKx is SYSCLK divided by 2 (default value for x 7)
  • 2 PBCLKx is SYSCLK divided by 3
  • 3 PBCLKx is SYSCLK divided by 4
  • 126 PBCLKx is SYSCLK divided by 127
  • 127 PBCLKx is SYSCLK divided by 128

PB8DIVPeripheral Bus x Clock Divisor Control Register (x = 1-7)

Address
0xBF801370
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
ON15Peripheral Bus x Output Clock Enable bit
  • 0 Output clock is disabled
  • 1 Output clock is enabled
PBDIVRDY11Peripheral Bus x Clock Divisor Ready bit
  • 0 Clock divisor logic is currently switching values and the PBxDIV bits cannot be written
  • 1 Clock divisor logic is not switching divisors and the PBxDIV bits may be written
PBDIV6:0Peripheral Bus x Clock Divisor Control bits
  • 0 PBCLKx is SYSCLK divided by 1 (default value for x = 7)
  • 1 PBCLKx is SYSCLK divided by 2 (default value for x 7)
  • 2 PBCLKx is SYSCLK divided by 3
  • 3 PBCLKx is SYSCLK divided by 4
  • 126 PBCLKx is SYSCLK divided by 127
  • 127 PBCLKx is SYSCLK divided by 128

SLEWCONOscillator Slew Control Register

Address
0xBF8013C0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
SYSDIV19:16System Clock Divide Control bits
  • 0 SYSCLK is not divided
  • 1 SYSCLK is divided by 2
  • 2 SYSCLK is divided by 3
  • 14 SYSCLK is divided by 15
  • 15 SYSCLK is divided by 16
SLWDIV10:8Slew Divisor Steps Control bits
  • 0 No divisor is used during slewing
  • 1 Steps are divide by 2
  • 2 Steps are divide by 4
  • 3 Steps are divide by 8
  • 4 Steps are divide by 16
  • 5 Steps are divide by 32
  • 6 Steps are divide by 64
  • 7 Steps are divide by 128
UPEN2Upward Slew Enable bit
  • 0 Slewing disabled for switching to a higher frequency
  • 1 Slewing enabled for switching to a higher frequency
DNEN1Downward Slew Enable bit
  • 0 Slewing disabled for switching to a lower frequency
  • 1 Slewing enabled for switching to a lower frequency
BUSY0Clock Switching Slewing Active Status bit
  • 0 Clock switch has reached its final value
  • 1 Clock frequency is being actively slewed to the new frequency

CLKSTATOscillator Clock Status Register

Address
0xBF8013D0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
LPRCRDY5Low-Power RC Oscillator Ready Status bit
  • 0 LPRC is disabled or not operating
  • 1 LPRC is stable and ready
SOSCRDY4Secondary Oscillator Ready Status bit
  • 0 Sosc is disabled or not operating
  • 1 Sosc is stable and ready
POSCRDY2Primary Oscillator Ready Status bit
  • 0 Posc is disabled or not operating
  • 1 Posc is stable and ready
SPDIVRDY1
FRCRDY0Fast RC Oscillator Ready Status bit
  • 0 FRC is disabled for not operating
  • 1 FRC is stable and ready