The 11 registers of PORTD (I/O port D), from 0xBF860310, with their reset value and every field. The PIC32MZ1024EFG064 has 1143 registers in 83 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
PORTD I/O port D
TRISD
Address
0xBF860310
Reset
0x00000E3F
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
TRISD11
11
TRISD10
10
TRISD9
9
TRISD5
5
TRISD4
4
TRISD3
3
TRISD2
2
TRISD1
1
TRISD0
0
PORTD
Address
0xBF860320
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
RD11
11
RD10
10
RD9
9
RD5
5
RD4
4
RD3
3
RD2
2
RD1
1
RD0
0
LATD
Address
0xBF860330
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
LATD11
11
LATD10
10
LATD9
9
LATD5
5
LATD4
4
LATD3
3
LATD2
2
LATD1
1
LATD0
0
ODCD
Address
0xBF860340
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
ODCD11
11
ODCD10
10
ODCD9
9
ODCD5
5
ODCD4
4
ODCD3
3
ODCD2
2
ODCD1
1
ODCD0
0
CNPUD
Address
0xBF860350
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
CNPUD11
11
CNPUD10
10
CNPUD9
9
CNPUD5
5
CNPUD4
4
CNPUD3
3
CNPUD2
2
CNPUD1
1
CNPUD0
0
CNPDD
Address
0xBF860360
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
CNPDD11
11
CNPDD10
10
CNPDD9
9
CNPDD5
5
CNPDD4
4
CNPDD3
3
CNPDD2
2
CNPDD1
1
CNPDD0
0
CNCONDChange Notice control for PORTx Register
Address
0xBF860370
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
ON
15
Change Notice Control ON bit
0 CN is disabled
1 CN is enabled
EDGEDETECT
11
Change Notification Style bit
0 Mismatch Style. Detect change from last PORTx read (CNSTATx used for CN Event).
1 Edge Style. Detect edge transitions (CNFx used for CN Event).
BETA