The 7 registers of DMT (Deadman timer), from 0xBF800A00, with their reset value and every field. The PIC32MZ1024EFG124 has 1300 registers in 90 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
DMT Deadman timer
DMTCONDeadman Timer Control Register
Address
0xBF800A00
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
ON
15
Deadman Timer Module Enable bit
0 Deadman Timer module is disabled
1 Deadman Timer module is enabled
DMTPRECLRDeadman Timer Preclear Register
Address
0xBF800A10
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
STEP1
15:8
Preclear Enable bits
64 Enables the Deadman Timer Preclear (Step 1)
DMTCLRDeadman Timer Clear Register
Address
0xBF800A20
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
STEP2
7:0
Clear Timer bits
8 Clears STEP1
DMTSTATDeadman Timer Status Register
Address
0xBF800A30
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
BAD
7:6
DMTEVENT
5
Deadman Timer Event bit
0 Deadman timer even was not detected
1 Deadman timer event was detected (counter expired or bad STEP1 or STEP2 value was entered prior to counter increment)
WINOPN
0
Deadman Timer Clear Window bit
0 Deadman timer clear window is not open
1 Deadman timer clear window is open
DMTCNTDeadman Timer Count Register
Address
0xBF800A40
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
COUNTER
31:0
DMTPSCNTPost Status Configure DMT Count Status Register
Address
0xBF800A60
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
PSCNT
31:0
DMTPSINTVPost Status Configure DMT Interval Status Register
BETA