The 6 registers of CFG (Configuration and pin control), from 0xBF800000, with their reset value and every field. The PIC32MZ1024EFG144 has 1315 registers in 91 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
CFG Configuration and pin control
CFGCONConfiguration Control Register
Address
0xBF800000
Reset
0x00000000
Access
read/write
Size
32-bit
13 fields
Field
Bits
What it does
DMAPRI
25
DMA Read and DMA Write Arbitration Priority to SRAM bit(1)
0 DMA uses Least Recently Serviced Arbitration (same as other initiators)
1 DMA gets High Priority access to SRAM
EXLPRI
24
ICACLK
17
Input Capture Alternate Clock Selection bit(1)
0 All Input Capture modules use Timer2/3 as their timebase clock
1 Input Capture modules use an alternative Timer pair as their timebase clock
OCACLK
16
Output Compare Alternate Clock Selection bit(1)
0 All Output Compare modules use Timer2/3 as their timebase clock
1 Output Compare modules use an alternative Timer pair as their timebase clock
IOLOCK
13
Peripheral Pin Select Lock bit(1)
0 Peripheral Pin Select is not locked. Writes to PPS registers are allowed
1 Peripheral Pin Select is locked. Writes to PPS registers are not allowed
PMDLOCK
12
Peripheral Module Disable bit(1)
0 Peripheral module is not locked. Writes to PMD registers are allowed
1 Peripheral module is locked. Writes to PMD registers are not allowed
PGLOCK
11
Permission Group Lock bit(1)
0 Permission Group registers are not locked. Writes to PG registers are allowed
1 Permission Group registers are locked. Writes to PG registers are not allowed
USBSSEN
8
USB Suspend Sleep Enable bit(1)
0 USB PHY clock continues to run when Sleep is active
1 USB PHY clock is shut down when Sleep mode is active
IOANCPN
7
ECCCON
5:4
Flash ECC Configuration bits
0 Flash ECC is enabled (ECCCON bits are locked; disables word Flash writes)
1 Dynamic Flash ECC is enabled (ECCCON bits are locked)
2 ECC and dynamic ECC are disabled (ECCCON bits are locked)
3 ECC and dynamic ECC are disabled (ECCCON bits are writable)
JTAGEN
3
JTAG Port Enable bit
0 Disable the JTAG port
1 Enable the JTAG port
TROEN
2
Trace Output Enable bit
0 Disable trace outputs and stop trace clock
1 Enable trace outputs and start trace clock (trace probe must be present)
TDOEN
0
TDO Enable for 2-Wire JTAG
0 2-wire JTAG protocol does not use TDO
1 2-wire JTAG protocol uses TDO
DEVIDDevice and Revision ID Register
Address
0xBF800020
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
DEVID
27:0
VER
31:28
SYSKEY
Address
0xBF800030
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
SYSKEY
31:0
CFGEBIAExternal Bus Interface Address Pin Configuration Register
Address
0xBF8000C0
Reset
0x00000000
Access
read/write
Size
32-bit
25 fields
Field
Bits
What it does
EBIA23EN
23
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA22EN
22
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA21EN
21
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA20EN
20
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA19EN
19
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA18EN
18
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA17EN
17
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA16EN
16
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA15EN
15
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA14EN
14
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA13EN
13
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA12EN
12
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA11EN
11
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA10EN
10
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA9EN
9
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA8EN
8
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA7EN
7
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA6EN
6
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA5EN
5
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA4EN
4
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA3EN
3
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA2EN
2
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA1EN
1
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIA0EN
0
EBI Address Pin Enable bits
0 EBIAx pin has is available for general use
1 EBIAx pin is enabled for use by EBI
EBIPINEN
31
EBI Pin Enable bit
0 Pins shared with EBI are available for general use
1 EBI controls access of pins shared with PMP
CFGEBICExternal Bus Interface Control Pin Configuration Register
Address
0xBF8000D0
Reset
0x00000000
Access
read/write
Size
32-bit
18 fields
Field
Bits
What it does
EBIRDYINV2
30
EBIRDY2 Inversion Control bit
0 Do not invert EBIRDY2 pin before use
1 Invert EBIRDY2 pin before use
EBIRDYINV1
29
EBIRDY1 Inversion Control bit
0 Do not invert EBIRDY1 pin before use
1 Invert EBIRDY1 pin before use
EBIRDYEN3
27
EBIRDY3 Pin Enable bit
0 EBIRDY3 pin is available for general use
1 EBIRDY3 pin is enabled for use by the EBI module
EBIRDYEN2
26
EBIRDY2 Pin Enable bit
0 EBIRDY2 pin is available for general use
1 EBIRDY2 pin is enabled for use by the EBI module
EBIRDYEN1
25
EBIRDY1 Pin Enable bit
0 EBIRDY1 pin is available for general use
1 EBIRDY1 pin is enabled for use by the EBI module
EBIRDYLVL
17
EBIRDYx Pin Sensitivity Control bit
0 Use edge detect for EBIRDYx pins
1 Use level detect for EBIRDYx pins
EBIRPEN
16
/EBIRP Pin Sensitivity Control bit
0 /EBIRP pin is available for general use
1 /EBIRP pin is enabled for use by the EBI module
EBIWEEN
13
/EBIWE Pin Enable bit
0 /EBIWE pin is available for general use
1 /EBIWE pin is enabled for use by the EBI module
EBIOEEN
12
/EBIOE Pin Enable bit
0 /EBIOE pin is available for general use
1 /EBIOE pin is enabled for use by the EBI module
EBIBSEN1
9
/EBIBS1 Pin Enable bit
0 /EBIBS1 pin is available for general use
1 /EBIBS1 pin is enabled for use by the EBI module
EBIBSEN0
8
/EBIBS0 Pin Enable bit
0 /EBIBS0 pin is available for general use
1 /EBIBS0 pin is enabled for use by the EBI module
EBICSEN3
7
/EBICS3 Pin Enable bit
0 /EBICS3 pin is available for general use
1 /EBICS3 pin is enabled for use by the EBI module
EBICSEN2
6
/EBICS2 Pin Enable bit
0 /EBICS2 pin is available for general use
1 /EBICS2 pin is enabled for use by the EBI module
EBICSEN1
5
/EBICS1 Pin Enable bit
0 /EBICS1 pin is available for general use
1 /EBICS1 pin is enabled for use by the EBI module
EBICSEN0
4
/EBICS0 Pin Enable bit
0 /EBICS0 pin is available for general use
1 /EBICS0 pin is enabled for use by the EBI module