PIC32MZ1024EFK124 CFG registers

The 6 registers of CFG (Configuration and pin control), from 0xBF800000, with their reset value and every field. The PIC32MZ1024EFK124 has 1675 registers in 93 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

CFG Configuration and pin control

CFGCONConfiguration Control Register

Address
0xBF800000
Reset
0x00000000
Access
read/write
Size
32-bit
13 fields
FieldBitsWhat it does
DMAPRI25DMA Read and DMA Write Arbitration Priority to SRAM bit(1)
  • 0 DMA uses Least Recently Serviced Arbitration (same as other initiators)
  • 1 DMA gets High Priority access to SRAM
EXLPRI24
ICACLK17Input Capture Alternate Clock Selection bit(1)
  • 0 All Input Capture modules use Timer2/3 as their timebase clock
  • 1 Input Capture modules use an alternative Timer pair as their timebase clock
OCACLK16Output Compare Alternate Clock Selection bit(1)
  • 0 All Output Compare modules use Timer2/3 as their timebase clock
  • 1 Output Compare modules use an alternative Timer pair as their timebase clock
IOLOCK13Peripheral Pin Select Lock bit(1)
  • 0 Peripheral Pin Select is not locked. Writes to PPS registers are allowed
  • 1 Peripheral Pin Select is locked. Writes to PPS registers are not allowed
PMDLOCK12Peripheral Module Disable bit(1)
  • 0 Peripheral module is not locked. Writes to PMD registers are allowed
  • 1 Peripheral module is locked. Writes to PMD registers are not allowed
PGLOCK11Permission Group Lock bit(1)
  • 0 Permission Group registers are not locked. Writes to PG registers are allowed
  • 1 Permission Group registers are locked. Writes to PG registers are not allowed
USBSSEN8USB Suspend Sleep Enable bit(1)
  • 0 USB PHY clock continues to run when Sleep is active
  • 1 USB PHY clock is shut down when Sleep mode is active
IOANCPN7
ECCCON5:4Flash ECC Configuration bits
  • 0 Flash ECC is enabled (ECCCON bits are locked; disables word Flash writes)
  • 1 Dynamic Flash ECC is enabled (ECCCON bits are locked)
  • 2 ECC and dynamic ECC are disabled (ECCCON bits are locked)
  • 3 ECC and dynamic ECC are disabled (ECCCON bits are writable)
JTAGEN3JTAG Port Enable bit
  • 0 Disable the JTAG port
  • 1 Enable the JTAG port
TROEN2Trace Output Enable bit
  • 0 Disable trace outputs and stop trace clock
  • 1 Enable trace outputs and start trace clock (trace probe must be present)
TDOEN0TDO Enable for 2-Wire JTAG
  • 0 2-wire JTAG protocol does not use TDO
  • 1 2-wire JTAG protocol uses TDO

DEVIDDevice and Revision ID Register

Address
0xBF800020
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
DEVID27:0
VER31:28

SYSKEY

Address
0xBF800030
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SYSKEY31:0

CFGEBIAExternal Bus Interface Address Pin Configuration Register

Address
0xBF8000C0
Reset
0x00000000
Access
read/write
Size
32-bit
21 fields
FieldBitsWhat it does
EBIA19EN19EBI Address Pin Enable bits
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA18EN18EBI Address Pin Enable bits
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA17EN17EBI Address Pin Enable bits
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA16EN16EBI Address Pin Enable bits
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA15EN15EBI Address Pin Enable bits
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA14EN14EBI Address Pin Enable bits
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA13EN13EBI Address Pin Enable bits
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA12EN12EBI Address Pin Enable bits
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA11EN11EBI Address Pin Enable bits
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA10EN10EBI Address Pin Enable bits
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA9EN9EBI Address Pin Enable bits
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA8EN8EBI Address Pin Enable bits
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA7EN7EBI Address Pin Enable bits
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA6EN6EBI Address Pin Enable bits
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA5EN5EBI Address Pin Enable bits
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA4EN4EBI Address Pin Enable bits
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA3EN3EBI Address Pin Enable bits
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA2EN2EBI Address Pin Enable bits
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA1EN1EBI Address Pin Enable bits
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA0EN0EBI Address Pin Enable bits
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIPINEN31EBI Pin Enable bit
  • 0 Pins shared with EBI are available for general use
  • 1 EBI controls access of pins shared with PMP

CFGEBICExternal Bus Interface Control Pin Configuration Register

Address
0xBF8000D0
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
EBIRDYINV230EBIRDY2 Inversion Control bit
  • 0 Do not invert EBIRDY2 pin before use
  • 1 Invert EBIRDY2 pin before use
EBIRDYINV129EBIRDY1 Inversion Control bit
  • 0 Do not invert EBIRDY1 pin before use
  • 1 Invert EBIRDY1 pin before use
EBIRDYEN327EBIRDY3 Pin Enable bit
  • 0 EBIRDY3 pin is available for general use
  • 1 EBIRDY3 pin is enabled for use by the EBI module
EBIRDYEN226EBIRDY2 Pin Enable bit
  • 0 EBIRDY2 pin is available for general use
  • 1 EBIRDY2 pin is enabled for use by the EBI module
EBIRDYEN125EBIRDY1 Pin Enable bit
  • 0 EBIRDY1 pin is available for general use
  • 1 EBIRDY1 pin is enabled for use by the EBI module
EBIRDYLVL17EBIRDYx Pin Sensitivity Control bit
  • 0 Use edge detect for EBIRDYx pins
  • 1 Use level detect for EBIRDYx pins
EBIWEEN13/EBIWE Pin Enable bit
  • 0 /EBIWE pin is available for general use
  • 1 /EBIWE pin is enabled for use by the EBI module
EBIOEEN12/EBIOE Pin Enable bit
  • 0 /EBIOE pin is available for general use
  • 1 /EBIOE pin is enabled for use by the EBI module
EBICSEN04/EBICS0 Pin Enable bit
  • 0 /EBICS0 pin is available for general use
  • 1 /EBICS0 pin is enabled for use by the EBI module
EBIDEN11EBI Data Upper Byte Pin Enable bit
  • 0 EBID pins have reverted to general use
  • 1 EBID pins are enabled for use by the EBI module
EBIDEN00EBI Data Lower Byte Pin Enable bit
  • 0 EBID pins have reverted to general use
  • 1 EBID pins are enabled for use by the EBI module
EBIRDYINV331EBIRDY3 Inversion Control bit
  • 0 Do not invert EBIRDY3 pin before use
  • 1 Invert EBIRDY3 pin before use

CFGPGPermission Group Configuration Register

Address
0xBF8000E0
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
FieldBitsWhat it does
CRYPTPG25:24Crypto Engine Permission Group bits
  • 0 Initiator is assigned to Permission Group 0
  • 1 Initiator is assigned to Permission Group 1
  • 2 Initiator is assigned to Permission Group 2
  • 3 Initiator is assigned to Permission Group 3
FCPG23:22
SQI1PG21:20
ETHPG17:16
CAN2PG15:14
CAN1PG13:12
USBPG9:8
DMAPG5:4
CPUPG1:0
ICD1PG31:30