The 12 registers of PORTH (I/O port H), from 0xBF860700, with their reset value and every field. The PIC32MZ1024EFK144 has 1692 registers in 94 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
PORTH I/O port H
ANSELH
Address
0xBF860700
Reset
0x00000073
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
ANSH6
6
ANSH5
5
ANSH4
4
ANSH1
1
ANSH0
0
TRISH
Address
0xBF860710
Reset
0x0000FFFF
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
TRISH15
15
TRISH14
14
TRISH13
13
TRISH12
12
TRISH11
11
TRISH10
10
TRISH9
9
TRISH8
8
TRISH7
7
TRISH6
6
TRISH5
5
TRISH4
4
TRISH3
3
TRISH2
2
TRISH1
1
TRISH0
0
PORTH
Address
0xBF860720
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
RH15
15
RH14
14
RH13
13
RH12
12
RH11
11
RH10
10
RH9
9
RH8
8
RH7
7
RH6
6
RH5
5
RH4
4
RH3
3
RH2
2
RH1
1
RH0
0
LATH
Address
0xBF860730
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
LATH15
15
LATH14
14
LATH13
13
LATH12
12
LATH11
11
LATH10
10
LATH9
9
LATH8
8
LATH7
7
LATH6
6
LATH5
5
LATH4
4
LATH3
3
LATH2
2
LATH1
1
LATH0
0
ODCH
Address
0xBF860740
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
ODCH15
15
ODCH14
14
ODCH13
13
ODCH12
12
ODCH11
11
ODCH10
10
ODCH9
9
ODCH8
8
ODCH7
7
ODCH6
6
ODCH5
5
ODCH4
4
ODCH3
3
ODCH2
2
ODCH1
1
ODCH0
0
CNPUH
Address
0xBF860750
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
CNPUH15
15
CNPUH14
14
CNPUH13
13
CNPUH12
12
CNPUH11
11
CNPUH10
10
CNPUH9
9
CNPUH8
8
CNPUH7
7
CNPUH6
6
CNPUH5
5
CNPUH4
4
CNPUH3
3
CNPUH2
2
CNPUH1
1
CNPUH0
0
CNPDH
Address
0xBF860760
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
CNPDH15
15
CNPDH14
14
CNPDH13
13
CNPDH12
12
CNPDH11
11
CNPDH10
10
CNPDH9
9
CNPDH8
8
CNPDH7
7
CNPDH6
6
CNPDH5
5
CNPDH4
4
CNPDH3
3
CNPDH2
2
CNPDH1
1
CNPDH0
0
CNCONHChange Notice control for PORTx Register
Address
0xBF860770
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
ON
15
Change Notice Control ON bit
0 CN is disabled
1 CN is enabled
EDGEDETECT
11
Change Notification Style bit
0 Mismatch Style. Detect change from last PORTx read (CNSTATx used for CN Event).
1 Edge Style. Detect edge transitions (CNFx used for CN Event).
BETA