PIC32MZ1025DAB176 USB registers

The 109 registers of USB (USB), from 0xBF884000, with their reset value and every field. The PIC32MZ1025DAB176 has 2254 registers in 102 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

USB USB

USBCRCONUSB Clock/Reset Control Register

Address: 0xBF884000
Reset: 0x00000000
Access: read/write
Size: 32-bit

13 fields

Field	Bits	What it does
USBIF	26	USB General Interrupt Flag bit `0` No interrupt from USB module or interrupts have not been enabled `1` An event on the USB Bus has occurred
USBRF	25	USB Resume Flag bit `0` No Resume activity detected during Suspend `1` Resume from Suspend state. Device wake-up activity can be started.
USBWKUP	24
USBIDOVEN	9	USB ID Override Enable bit `0` Disable use of USBIDVAL and instead use the PHY value `1` Enable use of USBIDVAL bit
USBIDVAL	8	USB ID Value bit `0` ID override value is 0 `1` ID override value is 1
PHYIDEN	7	PHY ID Monitoring Enable bit `0` Disable monitoring of the ID bit from the USB PHY `1` Enable monitoring of the ID bit from the USB PHY
VBUSMONEN	6	Vbus Monitoring for OTG Enable bit `0` Disable monitoring for Vbus in VBUS Valid range `1` Enable monitoring for Vbus in VBUS Valid range (between 4.4V and 4.75V)
ASVALMONEN	5	A-Device Vbus Monitoring for OTG Enable bit `0` Disable monitoring for Vbus in Session Valid range for A-device `1` Enable monitoring for Vbus in Session Valid range for A-device (between 0.8V and 2.0V)
BSVALMONEN	4	B-Device Vbus Monitoring for OTG Enable bit `0` Disable monitoring for Vbus in Session Valid range for B-device `1` Enable monitoring for Vbus in Session Valid range for B-device (between 0.8V and 4.0V)
SENDMONEN	3	Session End Vbus Monitoring for OTG Enable bit `0` Disable monitoring for Vbus in Session End range `1` Enable monitoring for Vbus in Session End range (between 0.2V and 0.8V)
USBIE	2	USB General Interrupt Enable bit `0` Disables general interrupt from USB module `1` Enables general interrupt from USB module
USBRIE	1	USB Resume Interrupt Enable bit `0` Disable interrupt to a Remote Devices USB resume signaling `1` Enable remote resume from suspend Interrupt
USBWKUPEN	0	USB Activity Detection Interrupt Enable bit `0` Disable interrupt for detection of activity on USB bus in Sleep mode `1` Enable interrupt for detection of activity on USB bus in Sleep mode

USBCSR0USB Control Status Register 0

Address: 0xBF8E3000
Reset: 0x00000200
Access: read/write
Size: 32-bit

17 fields

Field	Bits	What it does
EP7TXIF	23	Endpoint 7 TX Interrupt Flag bit `0` No interrupt event `1` Endpoint has a transmit interrupt to be serviced
EP6TXIF	22	Endpoint 6 TX Interrupt Flag bit `0` No interrupt event `1` Endpoint has a transmit interrupt to be serviced
EP5TXIF	21	Endpoint 5 TX Interrupt Flag bit `0` No interrupt event `1` Endpoint has a transmit interrupt to be serviced
EP4TXIF	20	Endpoint 4 TX Interrupt Flag bit `0` No interrupt event `1` Endpoint has a transmit interrupt to be serviced
EP3TXIF	19	Endpoint 3 TX Interrupt Flag bit `0` No interrupt event `1` Endpoint has a transmit interrupt to be serviced
EP2TXIF	18	Endpoint 2 TX Interrupt Flag bit `0` No interrupt event `1` Endpoint has a transmit interrupt to be serviced
EP1TXIF	17	Endpoint 1 TX Interrupt Flag bit `0` No interrupt event `1` Endpoint has a transmit interrupt to be serviced
EP0IF	16	Endpoint 0 Interrupt bit `0` No interrupt event `1` Endpoint 0 has an interrupt to be serviced
ISOUPD	15	ISO Update bit ( `0` No change in behavior `1` USB module will wait for a SOF token from the time TXPKTRDY is set before sending the packet
SOFTCONN	14	Soft Connect/Disconnect Feature Selection bit `0` The USB D+/D- lines are disabled and are tri-stated `1` The USB D+/D- lines are enabled and active
HSEN	13	Hi-Speed Enable bit `0` Module only operates in Full-Speed mode `1` The USB module will negotiate for Hi-Speed mode when the device is reset by the hub
HSMODE	12	Hi-Speed Mode Status bit `0` Module is not in Hi-Speed mode `1` Hi-Speed mode successfully negotiated during USB reset
RESET	11	Module Reset Status bit `0` Normal module operation `1` Reset signaling is present on the bus
RESUME	10	Resume from Suspend control bit `0` Stop Resume signaling `1` Generate Resume signaling when the device is in Suspend mode
SUSPMODE	9	Suspend Mode status bit `0` The USB module is in Normal operations `1` The USB module is in Suspend mode
SUSPEN	8	Suspend Mode Enable bit `0` Suspend mode is not enabled `1` Suspend mode is enabled
FUNC	6:0

USBCSR1USB Control Status Register 1

Address: 0xBF8E3004
Reset: 0x000000FF
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
EP7TXIE	23	Endpoint 7 Transmit Interrupt Enable bits `0` Endpoint Transmit interrupt events are not enabled `1` Endpoint Transmit interrupt events are enabled
EP6TXIE	22	Endpoint 6 Transmit Interrupt Enable bits `0` Endpoint Transmit interrupt events are not enabled `1` Endpoint Transmit interrupt events are enabled
EP5TXIE	21	Endpoint 5 Transmit Interrupt Enable bits `0` Endpoint Transmit interrupt events are not enabled `1` Endpoint Transmit interrupt events are enabled
EP4TXIE	20	Endpoint 4 Transmit Interrupt Enable bits `0` Endpoint Transmit interrupt events are not enabled `1` Endpoint Transmit interrupt events are enabled
EP3TXIE	19	Endpoint 3 Transmit Interrupt Enable bits `0` Endpoint Transmit interrupt events are not enabled `1` Endpoint Transmit interrupt events are enabled
EP2TXIE	18	Endpoint 2 Transmit Interrupt Enable bits `0` Endpoint Transmit interrupt events are not enabled `1` Endpoint Transmit interrupt events are enabled
EP1TXIE	17	Endpoint 1 Transmit Interrupt Enable bits `0` Endpoint Transmit interrupt events are not enabled `1` Endpoint Transmit interrupt events are enabled
EP0IE	16	Endpoint 0 Interrupt Enable bit `0` Endpoint 0 interrupt events are not enabled `1` Endpoint 0 interrupt events are enabled
EP7RXIF	7	Endpoint 7 RX Interrupt bit `0` No interrupt event `1` Endpoint has a receive event to be serviced
EP6RXIF	6	Endpoint 6 RX Interrupt bit `0` No interrupt event `1` Endpoint has a receive event to be serviced
EP5RXIF	5	Endpoint 5 RX Interrupt bit `0` No interrupt event `1` Endpoint has a receive event to be serviced
EP4RXIF	4	Endpoint 4 RX Interrupt bit `0` No interrupt event `1` Endpoint has a receive event to be serviced
EP3RXIF	3	Endpoint 3 RX Interrupt bit `0` No interrupt event `1` Endpoint has a receive event to be serviced
EP2RXIF	2	Endpoint 2 RX Interrupt bit `0` No interrupt event `1` Endpoint has a receive event to be serviced
EP1RXIF	1	Endpoint 1 RX Interrupt bit `0` No interrupt event `1` Endpoint has a receive event to be serviced

USBCSR2USB Control Status Register 2

Address: 0xBF8E3008
Reset: 0x060000FE
Access: read/write
Size: 32-bit

23 fields

Field	Bits	What it does
SESSRQIE	30	Session Request Interrupt Enable bit `0` Session request interrupt is disabled `1` Session request interrupt is enabled
DISCONIE	29	Device Disconnect Interrupt Enable bit `0` Device disconnect interrupt is disabled `1` Device disconnect interrupt is enabled
CONNIE	28	Device Connection Interrupt Enable bit `0` Device connection interrupt is disabled `1` Device connection interrupt is enabled
SOFIE	27	Start of Frame Interrupt Enable bit `0` Start of Frame event interrupt is disabled `1` Start of Frame event interrupt is enabled
RESETIE	26	Reset/Babble Interrupt Enable bit `0` Reset/Babble interrupt is disabled `1` Interrupt when reset (
RESUMEIE	25	Resume Interrupt Enable bit `0` Resume signaling interrupt is disabled `1` Resume signaling interrupt is enabled
SUSPIE	24	Suspend Interrupt Enable bit `0` Suspend signaling interrupt is disabled `1` Suspend signaling interrupt is enabled
VBUSERRIF	23	Vbus Error Interrupt bit `0` No interrupt `1` Vbus has dropped below the Vbus valid threshold during a session
SESSRQIF	22	Session Request Interrupt bit `0` No session request detected `1` Session request signaling has been detected
DISCONIF	21	Device Disconnect Interrupt bit `0` No device disconnect detected `1` In Host mode
CONNIF	20	Device Connection Interrupt bit `0` No device connection detected `1` In Host mode
SOFIF	19	Start of Frame Interrupt bit `0` No start of frame detected `1` A new frame has started
RESETIF	18	Reset/Babble Interrupt bit `0` No reset/babble detected `1` (In Host mode): indicates babble is detected / (In Device mode): indicates reset signaling is detected on the bus.
RESUMEIF	17	Resume Interrupt bit `0` No Resume signaling detected `1` Resume signaling is detected on the bus while USB module is in Suspend mode
SUSPIF	16	Suspend Interrupt bit `0` No suspend signaling detected `1` Suspend signaling is detected on the bus (Device mode)
EP7RXIE	7	Endpoint 7 Receive Interrupt Enable bit `0` Receive interrupt is not enabled `1` Receive interrupt is enabled for this endpoint
EP6RXIE	6	Endpoint 6 Receive Interrupt Enable bit `0` Receive interrupt is not enabled `1` Receive interrupt is enabled for this endpoint
EP5RXIE	5	Endpoint 5 Receive Interrupt Enable bit `0` Receive interrupt is not enabled `1` Receive interrupt is enabled for this endpoint
EP4RXIE	4	Endpoint 4 Receive Interrupt Enable bit `0` Receive interrupt is not enabled `1` Receive interrupt is enabled for this endpoint
EP3RXIE	3	Endpoint 3 Receive Interrupt Enable bit `0` Receive interrupt is not enabled `1` Receive interrupt is enabled for this endpoint
EP2RXIE	2	Endpoint 2 Receive Interrupt Enable bit `0` Receive interrupt is not enabled `1` Receive interrupt is enabled for this endpoint
EP1RXIE	1	Endpoint 1 Receive Interrupt Enable bit `0` Receive interrupt is not enabled `1` Receive interrupt is enabled for this endpoint
VBUSERRIE	31	Vbus Error Interrupt Enable bit `0` Vbus error interrupt is disabled `1` Vbus error interrupt is enabled

USBCSR3USB Control Status Register 3

Address: 0xBF8E300C
Reset: 0x00000000
Access: read/write
Size: 32-bit

10 fields

Field	Bits	What it does
FIFOACC	30	Test Mode Endpoint 0 FIFO Transfer Force bit `0` No transfer `1` Transfers the packet in the Endpoint 0 TX FIFO to the Endpoint 0 RX FIFO
FORCEFS	29	Test mode Force Full-Speed Mode Select bit `0` (If FORCEHS is 0): places USB module into Low-Speed mode. `1` Forces USB module into Full-Speed mode. Undefined behavior if FORCEHS is 1
FORCEHS	28	Test mode Force Hi-Speed Mode Select bit `0` If FORCEFS is 0 `1` Forces USB module into Hi-Speed mode. Undefined behavior if FORCEFS = 1.
PACKET	27	Test_Packet Test Mode Select bit `0` Normal operation `1` The USB module repetitively transmits on the bus a 53-byte test packet. Test packet must be loaded into the Endpoint 0 FIFO before the test mode is entered.
TESTK	26	Test_K Test Mode Select bit `0` Normal operation `1` Enters Test_K test mode. The USB module transmits a continuous K on the bus.
TESTJ	25	Test_J Test Mode Select bit `0` Normal operation `1` Enters Test_J test mode. The USB module transmits a continuous J on the bus.
NAK	24	Test_SE0_NAK Test Mode Select bit `0` Normal operation `1` Enter Test_SE0_NAK test mode. The USB module remains in Hi-Speed mode but responds to any valid IN token with a NAK
ENDPOINT	19:16	Endpoint Registers Select bits `0` Endpoint 0 `1` Endpoint 1 `2` Endpoint 2 `3` Endpoint 3 `4` Endpoint 4 `5` Endpoint 5 `6` Endpoint 6 `7` Endpoint 7 `8` Reserved `9` Reserved `10` Reserved `11` Reserved `12` Reserved `13` Reserved `14` Reserved `15` Reserved
RFRMNUM	10:0
FORCEHST	31	Test Mode Force Host Select bit `0` Normal operation `1` Forces USB module into Host mode

USBIE0CSR0USB Indexed Endpoint Control Status Register 0 (Endpoint 0)

Address: 0xBF8E3010
Reset: 0x00000000
Access: read/write
Size: 32-bit

12 fields

Field	Bits	What it does
DTWE	26
DT	25
FLUSH	24
NAKTO	23
STATUS	22
REQPKT	21
ERROR	20
SETUP	19
STALLED	18
TXRDY	17
RXRDY	16
TXMAXP	10:0

USBIENCSR0USB Indexed Endpoint Control Status Register 0 (Endpoint 1-7)

Address: 0xBF8E3010
Reset: 0x00000000
Access: read/write
Size: 32-bit

17 fields

Field	Bits	What it does
MODE	29	Endpoint Direction Control bit `0` Endpoint is RX `1` Endpoint is TX
DMAREQEN	28	Endpoint DMA Request Enable bit `0` DMA requests are disabled for this endpoint `1` DMA requests are enabled for this endpoint
FRCDATTG	27	Force Endpoint Data Toggle Control bit `0` No forced behavior `1` Forces the endpoint data toggle to switch and the data packet to be cleared from the FIFO
DMAREQMD	26	Endpoint DMA Request Mode Control bit `0` DMA Request Mode 0 `1` DMA Request Mode 1
DTWREN	25
DATATGGL	24
NAKTMOUT	23	Incomplete TX Status bit `0` Meaning of bitfield depends on Host / Device mode of operation. `1` Meaning of bitfield depends on Host / Device mode of operation.
CLRDT	22	Clear Data Toggle Control bit `0` Do not clear the data toggle `1` Resets the endpoint data toggle to 0
RXSTALL	21	STALL handshake transmission status bit `0` Meaning of bitfield depends on Host / Device mode of operation `1` Meaning of bitfield depends on Host / Device mode of operation.
SETUPPKT	20	STALL handshake transmission control bit `0` Meaning of bitfield depends on Host / Device mode of operation `1` Meaning of bitfield depends on Host / Device mode of operation
FLUSH	19	FIFO Flush control bit `0` Do not flush the FIFO `1` Flush the latest packet from the endpoint TX FIFO. The FIFO pointer is reset
ERROR	18	Underrun status bit `0` Meaning of bitfield depends on Host / Device mode of operation. `1` Meaning of bitfield depends on Host / Device mode of operation.
FIFONE	17	FIFO Not Empty status bit `0` TX FIFO is empty `1` There is at least 1 packet in the TX FIFO
TXPKTRDY	16
MULT	15:11
TXMAXP	10:0
AUTOSET	31	Auto Set Control bit `0` TXPKTRDY must be set manually for all packet sizes `1` TXPKTRDY will be automatically set when data of the maximum packet size (value in TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded

USBIENCSR1USB Indexed Endpoint Control Status Register 1 (Endpoint 1-7)

Address: 0xBF8E3014
Reset: 0x00000000
Access: read/write
Size: 32-bit

18 fields

Field	Bits	What it does
AUTORQ	30	Isochronous Endpoint Control bit `0` Meaning of bitfield depends on Host / Device mode of operation `1` Meaning of bitfield depends on Host / Device mode of operation
DMAREQEN	29	DMA Request Enable Control bit `0` Disable DMA requests for the RX endpoint. `1` Enable DMA requests for the RX endpoint.
PIDERR	28	Disable NYET Handshakes Control/PID Error Status bit `0` Meaning of bitfield depends on Host / Device mode of operation. `1` Meaning of bitfield depends on Host / Device mode of operation.
DMAREQMD	27	DMA Request Mode Selection bit `0` DMA Request Mode 0 `1` DMA Request Mode 1
DATATWEN	26	Data Toggle Write Enable Control bit ( `0` DATATGGL is not writable `1` DATATGGL can be written
DATATGGL	25
INCOMPRX	24	Incomplete Packet Status bit `0` Written by then software to clear this bit `1` The packet in the RX FIFO during a high-bandwidth Isochronous/Interrupt transfer is incomplete because parts of the data were not received
CLRDT	23	Clear Data Toggle Control bit `0` Leave endpoint data toggle alone `1` Reset the endpoint data toggle to 0
RXSTALL	22	STALL Handshake Status bit `0` Meaning of bitfield depends on Host / Device mode of operation `1` Meaning of bitfield depends on Host / Device mode of operation
REQPKT	21	STALL Handshake Control bit `0` Meaning of bitfield depends on Host / Device mode of operation `1` Meaning of bitfield depends on Host / Device mode of operation
FLUSH	20	Flush FIFO Control bit `0` Normal FIFO operation `1` Flush the next packet to be read from the endpoint RX FIFO. The FIFO pointer is reset and the RXPKTRDY bit is cleared. This should only be used when RXPKTRDY is set. If the FIFO is double-buffered
DERRNAKT	19	Data Packet Error Status bit `0` Meaning of bitfield depends on Host / Device mode of operation `1` Meaning of bitfield depends on Host / Device mode of operation.
ERROR	18	Data Overrun Status bit `0` Meaning of bitfield depends on Host / Device mode of operation `1` Meaning of bitfield depends on Host / Device mode of operation
FIFOFULL	17	FIFO Full Status bit `0` The RX FIFO has at least one free space `1` No more packets can be loaded into the RX FIFO
RXPKTRDY	16	Data Packet Reception Status bit `0` Written by software to clear this bit when the packet has been unloaded from the RX FIFO. `1` A data packet has been received. An interrupt is generated.
MULT	15:11
RXMAXP	10:0
AUTOCLR	31	RXPKTRDY Automatic Clear Control bit `0` No automatic clearing of RXPKTRDY `1` RXPKTRDY will be automatically cleared when a packet of RXMAXP bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded

USBIE0CSR2USB Indexed Endpoint Control Status Register 2 (Endpoint 0)

Address: 0xBF8E3018
Reset: 0x00000000
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
NAKLIM	27:24
SPEED	23:22	Operating Speed Control bits `0` Reserved `1` Hi-Speed `2` Full-Speed `3` Low-Speed
RXCNT	6:0

USBIENCSR2USB Indexed Endpoint Control Status Register 2 (Endpoint 1-7)

Address: 0xBF8E3018
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
SPEED	23:22	TX Endpoint Operating Speed Control bits ( `0` Reserved `1` Hi-Speed `2` Full-Speed `3` Low-Speed
PROTOCOL	21:20	TX Endpoint Protocol Control bits `0` Control `1` Isochronous `2` Bulk `3` Interrupt
TEP	19:16
RXCNT	13:0
TXINTERV	31:24

USBIE0CSR3USB Indexed Endpoint Control Status Register 3 (Endpoint 0)

Address: 0xBF8E301C
Reset: 0x00000000
Access: read only
Size: 32-bit

8 fields

Field	Bits	What it does
MPTXEN	30	Automatic Splitting Option bit `0` No automatic splitting `1` Automatic splitting of bulk packets is done
BIGEND	29	Byte Ordering Option bit `0` Little Endian ordering `1` Big Endian ordering
HBRXEN	28	High-bandwidth RX ISO Option bit `0` No High-bandwidth RX ISO support `1` High-bandwidth RX ISO endpoint support is selected
HBTXEN	27	High-bandwidth TX ISO Option bit `0` No High-bandwidth TX ISO support `1` High-bandwidth TX ISO endpoint support is selected
DYNFIFOS	26	Dynamic FIFO Sizing Option bit `0` No Dynamic FIFO sizing `1` Dynamic FIFO sizing is supported
SOFTCONE	25	Soft Connect/Disconnect Option bit `0` Soft Connect/Disconnect is not supported `1` Soft Connect/Disconnect is supported
UTMIDWID	24
MPRXEN	31	Automatic Amalgamation Option bit `0` No automatic amalgamation `1` Automatic amalgamation of bulk packets is done

USBIENCSR3USB Indexed Endpoint Control Status Register 3 (Endpoint 1-7)

Address: 0xBF8E301C
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
TXFIFOSZ	27:24	Transmit FIFO Size bits `0` Reserved or endpoint has not been configured `1` Reserved `2` Reserved `3` 8 bytes `4` 16 bytes `5` 32 bytes `6` 64 bytes `7` 128 bytes `8` 256 bytes `9` 512 bytes `10` 1024 bytes `11` 2048 bytes `12` 4096 bytes `13` 8192 bytes `14` Reserved `15` Reserved
RXINTERV	15:8
SPEED	7:6	RX Endpoint Operating Speed Control bits `0` Reserved `1` Hi-Speed `2` Full-Speed `3` Low-Speed
PROTOCOL	5:4	RX Endpoint Protocol Control bits `0` Control `1` Isochronous `2` Bulk `3` Interrupt
TEP	3:0
RXFIFOSZ	31:28	Receive FIFO Size bits `0` Reserved or endpoint has not been configured `1` Reserved `2` Reserved `3` 8 bytes `4` 16 bytes `5` 32 bytes `6` 64 bytes `7` 128 bytes `8` 256 bytes `9` 512 bytes `10` 1024 bytes `11` 2048 bytes `12` 4096 bytes `13` 8192 bytes `14` Reserved `15` Reserved

USBFIFO0USB FIFO Data Register x (x = 0-7

Address: 0xBF8E3020
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

USBFIFO1USB FIFO Data Register x (x = 0-7

Address: 0xBF8E3024
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

USBFIFO2USB FIFO Data Register x (x = 0-7

Address: 0xBF8E3028
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

USBFIFO3USB FIFO Data Register x (x = 0-7

Address: 0xBF8E302C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

USBFIFO4USB FIFO Data Register x (x = 0-7

Address: 0xBF8E3030
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

USBFIFO5USB FIFO Data Register x (x = 0-7

Address: 0xBF8E3034
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

USBFIFO6USB FIFO Data Register x (x = 0-7

Address: 0xBF8E3038
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

USBFIFO7USB FIFO Data Register x (x = 0-7

Address: 0xBF8E303C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

USBOTGUSB OTG Control/Status Register

Address: 0xBF8E3060
Reset: 0x00000080
Access: read/write
Size: 32-bit

13 fields

Field	Bits	What it does
RXDPB	28	RX Endpoint Double-packet Buffering Control bit `0` Double-packet buffer is not supported `1` Double-packet buffer is supported. This doubles the size set in RXFIFOSZ.
RXFIFOSZ	27:24	RX Endpoint FIFO Packet Size bits `0` 8 bytes `1` 16 bytes `2` 32 bytes `3` 64 bytes `4` 128 bytes `5` 256 bytes `6` 512 bytes `7` 1024 bytes `8` 2048 bytes `9` 4096 bytes `10` Reserved `11` Reserved `12` Reserved `13` Reserved `14` Reserved `15` Reserved
TXDPB	20	TX Endpoint Double-packet Buffering Control bit `0` Double-packet buffer is not supported `1` Double-packet buffer is supported. This doubles the size set in TXFIFOSZ.
TXFIFOSZ	19:16	TX Endpoint FIFO packet size bits `0` 8 bytes `1` 16 bytes `2` 32 bytes `3` 64 bytes `4` 128 bytes `5` 256 bytes `6` 512 bytes `7` 1024 bytes `8` 2048 bytes `9` 4096 bytes `10` Reserved `15` Reserved
TXEDMA	9	TX Endpoint DMA Assertion Control bit `0` DMA_REQ signal for all IN endpoints will be deasserted when MAXP bytes have been written to an endpoint. This is Late mode. `1` DMA_REQ signal for all IN endpoints will be deasserted when MAXP-8 bytes have been written to an endpoint. This is Early mode.
RXEDMA	8	RX Endpoint DMA Assertion Control bit `0` DMA_REQ signal for all OUT endpoints will be deasserted when MAXP bytes have been written to an endpoint. This is Late mode. `1` DMA_REQ signal for all OUT endpoints will be deasserted when MAXP-8 bytes have been written to an endpoint. This is Early mode.
BDEV	7	USB Device Type bit `0` USB is operating as an A device `1` USB is operating as a B device
FSDEV	6	Full-Speed/Hi-Speed device detection bit ( `0` No Full-Speed or Hi-Speed device detected `1` A Full-Speed or Hi-Speed device has been detected being connected to the port
LSDEV	5	Low-Speed Device Detection bit `0` No Low-Speed device detected `1` A Low-Speed device has been detected being connected to the port
VBUS	4:3	Vbus Level Detection bits `0` Below Session End `1` Above Session End `2` Above AValid `3` Above Vbus Valid
HOSTMODE	2	Host Mode bit `0` USB module is not acting as a Host `1` USB module is acting as a Host
HOSTREQ	1	Host Request Control bit `0` Host Negotiation is not taking place `1` USB module initiates the Host Negotiation when Suspend mode is entered. This bit is cleared when Host Negotiation is completed.
SESSION	0	Active Session Control/Status bit `0` (A device): End a session / (B device): When USB module is in Suspend mode `1` (A device): Start a session / (B device): Session has started or is in progress

USBFIFOAUSB FIFO Address Register

Address: 0xBF8E3064
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
RXFIFOAD	28:16	Receive Endpoint FIFO Address bits `0` 0x0000 `1` 0x0008 `2` 0x0010 `8191` 0xFFF8
TXFIFOAD	12:0	Transmit Endpoint FIFO Address bits `0` 0x0000 `1` 0x0008 `2` 0x0010 `8191` 0xFFF8

USBHWVERUSB Hardware Version Register

Address: 0xBF8E306C
Reset: 0x00000000
Access: read only
Size: 32-bit

3 fields

Field	Bits	What it does
RC	15	Release Candidate bit `0` USB module was created using a full release `1` USB module was created using a release candidate
VERMAJOR	14:10
VERMINOR	9:0

USBINFOUSB Information Register

Address: 0xBF8E3078
Reset: 0x3C5C8C77
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
WTCON	23:20
WTID	19:16
DMACHANS	15:12
RAMBITS	11:8
RXENDPTS	7:4
TXENDPTS	3:0
VPLEN	31:24

USBEOFRSTUSB End-of-Frame/Soft Reset Control Register

Address: 0xBF8E307C
Reset: 0x00727780
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
NRSTX	25	Reset of XCLK Domain bit
NRST	24	Reset of CLK Domain bit
LSEOF	23:16
FSEOF	15:8
HSEOF	7:0

USBE0TXAUSB Endpoint 0 Transmit Address Register

Address: 0xBF8E3080
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TXHUBPRT	30:24
MULTTRAN	23	TX Hub Multiple Translators bit `0` The USB 2.0 hub has a single transaction translator `1` The USB 2.0 hub has multiple transaction translators
TXHUBADD	22:16
TXFADDR	6:0

USBE0RXAUSB Endpoint 0 Receive Address Register

Address: 0xBF8E3084
Reset: 0x00000000
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
RXHUBPRT	30:24
MULTTRAN	23	RX Hub Multiple Translators bit `0` The USB 2.0 hub has a single transaction translator `1` The USB 2.0 hub has multiple transaction translators
RXHUBADD	22:16

USBE1TXAUSB Endpoint 1 Transmit Address Register

Address: 0xBF8E3088
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TXHUBPRT	30:24
MULTTRAN	23	TX Hub Multiple Translators bit `0` The USB 2.0 hub has a single transaction translator `1` The USB 2.0 hub has multiple transaction translators
TXHUBADD	22:16
TXFADDR	6:0

USBE1RXAUSB Endpoint 1 Receive Address Register

Address: 0xBF8E308C
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
RXHUBPRT	30:24
MULTTRAN	23	RX Hub Multiple Translators bit `0` The USB 2.0 hub has a single transaction translator `1` The USB 2.0 hub has multiple transaction translators
RXHUBADD	22:16
RXFADDR	6:0

USBE2TXAUSB Endpoint 2 Transmit Address Register

Address: 0xBF8E3090
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TXHUBPRT	30:24
MULTTRAN	23	TX Hub Multiple Translators bit `0` The USB 2.0 hub has a single transaction translator `1` The USB 2.0 hub has multiple transaction translators
TXHUBADD	22:16
TXFADDR	6:0

USBE2RXAUSB Endpoint 2 Receive Address Register

Address: 0xBF8E3094
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
RXHUBPRT	30:24
MULTTRAN	23	RX Hub Multiple Translators bit `0` The USB 2.0 hub has a single transaction translator `1` The USB 2.0 hub has multiple transaction translators
RXHUBADD	22:16
RXFADDR	6:0

USBE3TXAUSB Endpoint 3 Transmit Address Register

Address: 0xBF8E3098
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TXHUBPRT	30:24
MULTTRAN	23	TX Hub Multiple Translators bit `0` The USB 2.0 hub has a single transaction translator `1` The USB 2.0 hub has multiple transaction translators
TXHUBADD	22:16
TXFADDR	6:0

USBE3RXAUSB Endpoint 3 Receive Address Register

Address: 0xBF8E309C
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
RXHUBPRT	30:24
MULTTRAN	23	RX Hub Multiple Translators bit `0` The USB 2.0 hub has a single transaction translator `1` The USB 2.0 hub has multiple transaction translators
RXHUBADD	22:16
RXFADDR	6:0

USBE4TXAUSB Endpoint 4 Transmit Address Register

Address: 0xBF8E30A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TXHUBPRT	30:24
MULTTRAN	23	TX Hub Multiple Translators bit `0` The USB 2.0 hub has a single transaction translator `1` The USB 2.0 hub has multiple transaction translators
TXHUBADD	22:16
TXFADDR	6:0

USBE4RXAUSB Endpoint 4 Receive Address Register

Address: 0xBF8E30A4
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
RXHUBPRT	30:24
MULTTRAN	23	RX Hub Multiple Translators bit `0` The USB 2.0 hub has a single transaction translator `1` The USB 2.0 hub has multiple transaction translators
RXHUBADD	22:16
RXFADDR	6:0

USBE5TXAUSB Endpoint 5 Transmit Address Register

Address: 0xBF8E30A8
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TXHUBPRT	30:24
MULTTRAN	23	TX Hub Multiple Translators bit `0` The USB 2.0 hub has a single transaction translator `1` The USB 2.0 hub has multiple transaction translators
TXHUBADD	22:16
TXFADDR	6:0

USBE5RXAUSB Endpoint 5 Receive Address Register

Address: 0xBF8E30AC
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
RXHUBPRT	30:24
MULTTRAN	23	RX Hub Multiple Translators bit `0` The USB 2.0 hub has a single transaction translator `1` The USB 2.0 hub has multiple transaction translators
RXHUBADD	22:16
RXFADDR	6:0

USBE6TXAUSB Endpoint 6 Transmit Address Register

Address: 0xBF8E30B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TXHUBPRT	30:24
MULTTRAN	23	TX Hub Multiple Translators bit `0` The USB 2.0 hub has a single transaction translator `1` The USB 2.0 hub has multiple transaction translators
TXHUBADD	22:16
TXFADDR	6:0

USBE6RXAUSB Endpoint 6 Receive Address Register

Address: 0xBF8E30B4
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
RXHUBPRT	30:24
MULTTRAN	23	RX Hub Multiple Translators bit `0` The USB 2.0 hub has a single transaction translator `1` The USB 2.0 hub has multiple transaction translators
RXHUBADD	22:16
RXFADDR	6:0

USBE7TXAUSB Endpoint 7 Transmit Address Register

Address: 0xBF8E30B8
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TXHUBPRT	30:24
MULTTRAN	23	TX Hub Multiple Translators bit `0` The USB 2.0 hub has a single transaction translator `1` The USB 2.0 hub has multiple transaction translators
TXHUBADD	22:16
TXFADDR	6:0

USBE7RXAUSB Endpoint 7 Receive Address Register

Address: 0xBF8E30BC
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
RXHUBPRT	30:24
MULTTRAN	23	RX Hub Multiple Translators bit `0` The USB 2.0 hub has a single transaction translator `1` The USB 2.0 hub has multiple transaction translators
RXHUBADD	22:16
RXFADDR	6:0

USBE0CSR0

Address: 0xBF8E3100
Reset: 0x00000000
Access: read/write
Size: 32-bit

12 fields

Field	Bits	What it does
DTWE	26
DT	25
FLUSH	24
NAKTO	23
STATUS	22
REQPKT	21
ERROR	20
SETUP	19
STALLED	18
TXRDY	17
RXRDY	16
TXMAXP	10:0

USBE0CSR2

Address: 0xBF8E3108
Reset: 0x00000000
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
NAKLIM	27:24
SPEED	23:22
RXCNT	6:0

USBE0CSR3

Address: 0xBF8E310C
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
MPTXEN	30
BIGEND	29
HBRXEN	28
HBTXEN	27
DYNFIFOS	26
SOFTCONE	25
UTMIDWID	24
MPRXEN	31

USBE1CSR0

Address: 0xBF8E3110
Reset: 0x00000000
Access: read/write
Size: 32-bit

17 fields

Field	Bits	What it does
MODE	29
DMAREQEN	28
FRCDATTG	27
DMAREQMD	26
DTWREN	25
DATATGGL	24
NAKTMOUT	23
CLRDT	22
RXSTALL	21
SETUPPKT	20
FLUSH	19
ERROR	18
FIFONE	17
TXPKTRDY	16
MULT	15:11
TXMAXP	10:0
AUTOSET	31

USBE1CSR1

Address: 0xBF8E3114
Reset: 0x00000000
Access: read/write
Size: 32-bit

18 fields

Field	Bits	What it does
AUTORQ	30
DMAREQEN	29
PIDERR	28
DMAREQMD	27
DATATWEN	26
DATATGGL	25
INCOMPRX	24
CLRDT	23
RXSTALL	22
REQPKT	21
FLUSH	20
DERRNAKT	19
ERROR	18
FIFOFULL	17
RXPKTRDY	16
MULT	15:11
RXMAXP	10:0
AUTOCLR	31

USBE1CSR2

Address: 0xBF8E3118
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
SPEED	23:22
PROTOCOL	21:20
TEP	19:16
RXCNT	13:0
TXINTERV	31:24

USBE1CSR3

Address: 0xBF8E311C
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
TXFIFOSZ	27:24
RXINTERV	15:8
SPEED	7:6
PROTOCOL	5:4
TEP	3:0
RXFIFOSZ	31:28

USBE2CSR0

Address: 0xBF8E3120
Reset: 0x00000000
Access: read/write
Size: 32-bit

17 fields

Field	Bits	What it does
MODE	29
DMAREQEN	28
FRCDATTG	27
DMAREQMD	26
DTWREN	25
DATATGGL	24
NAKTMOUT	23
CLRDT	22
RXSTALL	21
SETUPPKT	20
FLUSH	19
ERROR	18
FIFONE	17
TXPKTRDY	16
MULT	15:11
TXMAXP	10:0
AUTOSET	31

USBE2CSR1

Address: 0xBF8E3124
Reset: 0x00000000
Access: read/write
Size: 32-bit

18 fields

Field	Bits	What it does
AUTORQ	30
DMAREQEN	29
PIDERR	28
DMAREQMD	27
DATATWEN	26
DATATGGL	25
INCOMPRX	24
CLRDT	23
RXSTALL	22
REQPKT	21
FLUSH	20
DERRNAKT	19
ERROR	18
FIFOFULL	17
RXPKTRDY	16
MULT	15:11
RXMAXP	10:0
AUTOCLR	31

USBE2CSR2

Address: 0xBF8E3128
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
SPEED	23:22
PROTOCOL	21:20
TEP	19:16
RXCNT	13:0
TXINTERV	31:24

USBE2CSR3

Address: 0xBF8E312C
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
TXFIFOSZ	27:24
RXINTERV	15:8
SPEED	7:6
PROTOCOL	5:4
TEP	3:0
RXFIFOSZ	31:28

USBE3CSR0

Address: 0xBF8E3130
Reset: 0x00000000
Access: read/write
Size: 32-bit

17 fields

Field	Bits	What it does
MODE	29
DMAREQEN	28
FRCDATTG	27
DMAREQMD	26
DTWREN	25
DATATGGL	24
NAKTMOUT	23
CLRDT	22
RXSTALL	21
SETUPPKT	20
FLUSH	19
ERROR	18
FIFONE	17
TXPKTRDY	16
MULT	15:11
TXMAXP	10:0
AUTOSET	31

USBE3CSR1

Address: 0xBF8E3134
Reset: 0x00000000
Access: read/write
Size: 32-bit

18 fields

Field	Bits	What it does
AUTORQ	30
DMAREQEN	29
PIDERR	28
DMAREQMD	27
DATATWEN	26
DATATGGL	25
INCOMPRX	24
CLRDT	23
RXSTALL	22
REQPKT	21
FLUSH	20
DERRNAKT	19
ERROR	18
FIFOFULL	17
RXPKTRDY	16
MULT	15:11
RXMAXP	10:0
AUTOCLR	31

USBE3CSR2

Address: 0xBF8E3138
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
SPEED	23:22
PROTOCOL	21:20
TEP	19:16
RXCNT	13:0
TXINTERV	31:24

USBE3CSR3

Address: 0xBF8E313C
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
TXFIFOSZ	27:24
RXINTERV	15:8
SPEED	7:6
PROTOCOL	5:4
TEP	3:0
RXFIFOSZ	31:28

USBE4CSR0

Address: 0xBF8E3140
Reset: 0x00000000
Access: read/write
Size: 32-bit

17 fields

Field	Bits	What it does
MODE	29
DMAREQEN	28
FRCDATTG	27
DMAREQMD	26
DTWREN	25
DATATGGL	24
NAKTMOUT	23
CLRDT	22
RXSTALL	21
SETUPPKT	20
FLUSH	19
ERROR	18
FIFONE	17
TXPKTRDY	16
MULT	15:11
TXMAXP	10:0
AUTOSET	31

USBE4CSR1

Address: 0xBF8E3144
Reset: 0x00000000
Access: read/write
Size: 32-bit

18 fields

Field	Bits	What it does
AUTORQ	30
DMAREQEN	29
PIDERR	28
DMAREQMD	27
DATATWEN	26
DATATGGL	25
INCOMPRX	24
CLRDT	23
RXSTALL	22
REQPKT	21
FLUSH	20
DERRNAKT	19
ERROR	18
FIFOFULL	17
RXPKTRDY	16
MULT	15:11
RXMAXP	10:0
AUTOCLR	31

USBE4CSR2

Address: 0xBF8E3148
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
SPEED	23:22
PROTOCOL	21:20
TEP	19:16
RXCNT	13:0
TXINTERV	31:24

USBE4CSR3

Address: 0xBF8E314C
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
TXFIFOSZ	27:24
RXINTERV	15:8
SPEED	7:6
PROTOCOL	5:4
TEP	3:0
RXFIFOSZ	31:28

USBE5CSR0

Address: 0xBF8E3150
Reset: 0x00000000
Access: read/write
Size: 32-bit

17 fields

Field	Bits	What it does
MODE	29
DMAREQEN	28
FRCDATTG	27
DMAREQMD	26
DTWREN	25
DATATGGL	24
NAKTMOUT	23
CLRDT	22
RXSTALL	21
SETUPPKT	20
FLUSH	19
ERROR	18
FIFONE	17
TXPKTRDY	16
MULT	15:11
TXMAXP	10:0
AUTOSET	31

USBE5CSR1

Address: 0xBF8E3154
Reset: 0x00000000
Access: read/write
Size: 32-bit

18 fields

Field	Bits	What it does
AUTORQ	30
DMAREQEN	29
PIDERR	28
DMAREQMD	27
DATATWEN	26
DATATGGL	25
INCOMPRX	24
CLRDT	23
RXSTALL	22
REQPKT	21
FLUSH	20
DERRNAKT	19
ERROR	18
FIFOFULL	17
RXPKTRDY	16
MULT	15:11
RXMAXP	10:0
AUTOCLR	31

USBE5CSR2

Address: 0xBF8E3158
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
SPEED	23:22
PROTOCOL	21:20
TEP	19:16
RXCNT	13:0
TXINTERV	31:24

USBE5CSR3

Address: 0xBF8E315C
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
TXFIFOSZ	27:24
RXINTERV	15:8
SPEED	7:6
PROTOCOL	5:4
TEP	3:0
RXFIFOSZ	31:28

USBE6CSR0

Address: 0xBF8E3160
Reset: 0x00000000
Access: read/write
Size: 32-bit

17 fields

Field	Bits	What it does
MODE	29
DMAREQEN	28
FRCDATTG	27
DMAREQMD	26
DTWREN	25
DATATGGL	24
NAKTMOUT	23
CLRDT	22
RXSTALL	21
SETUPPKT	20
FLUSH	19
ERROR	18
FIFONE	17
TXPKTRDY	16
MULT	15:11
TXMAXP	10:0
AUTOSET	31

USBE6CSR1

Address: 0xBF8E3164
Reset: 0x00000000
Access: read/write
Size: 32-bit

18 fields

Field	Bits	What it does
AUTORQ	30
DMAREQEN	29
PIDERR	28
DMAREQMD	27
DATATWEN	26
DATATGGL	25
INCOMPRX	24
CLRDT	23
RXSTALL	22
REQPKT	21
FLUSH	20
DERRNAKT	19
ERROR	18
FIFOFULL	17
RXPKTRDY	16
MULT	15:11
RXMAXP	10:0
AUTOCLR	31

USBE6CSR2

Address: 0xBF8E3168
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
SPEED	23:22
PROTOCOL	21:20
TEP	19:16
RXCNT	13:0
TXINTERV	31:24

USBE6CSR3

Address: 0xBF8E316C
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
TXFIFOSZ	27:24
RXINTERV	15:8
SPEED	7:6
PROTOCOL	5:4
TEP	3:0
RXFIFOSZ	31:28

USBE7CSR0

Address: 0xBF8E3170
Reset: 0x00000000
Access: read/write
Size: 32-bit

17 fields

Field	Bits	What it does
MODE	29
DMAREQEN	28
FRCDATTG	27
DMAREQMD	26
DTWREN	25
DATATGGL	24
NAKTMOUT	23
CLRDT	22
RXSTALL	21
SETUPPKT	20
FLUSH	19
ERROR	18
FIFONE	17
TXPKTRDY	16
MULT	15:11
TXMAXP	10:0
AUTOSET	31

USBE7CSR1

Address: 0xBF8E3174
Reset: 0x00000000
Access: read/write
Size: 32-bit

18 fields

Field	Bits	What it does
AUTORQ	30
DMAREQEN	29
PIDERR	28
DMAREQMD	27
DATATWEN	26
DATATGGL	25
INCOMPRX	24
CLRDT	23
RXSTALL	22
REQPKT	21
FLUSH	20
DERRNAKT	19
ERROR	18
FIFOFULL	17
RXPKTRDY	16
MULT	15:11
RXMAXP	10:0
AUTOCLR	31

USBE7CSR2

Address: 0xBF8E3178
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
SPEED	23:22
PROTOCOL	21:20
TEP	19:16
RXCNT	13:0
TXINTERV	31:24

USBE7CSR3

Address: 0xBF8E317C
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
TXFIFOSZ	27:24
RXINTERV	15:8
SPEED	7:6
PROTOCOL	5:4
TEP	3:0
RXFIFOSZ	31:28

USBDMAINTUSB DMA Interrupt Register

Address: 0xBF8E3200
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
DMA8IF	7	DMA Channel 8 Interrupt bit `0` No interrupt event `1` The DMA channel has an interrupt event
DMA7IF	6	DMA Channel 7 Interrupt bit `0` No interrupt event `1` The DMA channel has an interrupt event
DMA6IF	5	DMA Channel 6 Interrupt bit `0` No interrupt event `1` The DMA channel has an interrupt event
DMA5IF	4	DMA Channel 5 Interrupt bit `0` No interrupt event `1` The DMA channel has an interrupt event
DMA4IF	3	DMA Channel 4 Interrupt bit `0` No interrupt event `1` The DMA channel has an interrupt event
DMA3IF	2	DMA Channel 3 Interrupt bit `0` No interrupt event `1` The DMA channel has an interrupt event
DMA2IF	1	DMA Channel 2 Interrupt bit `0` No interrupt event `1` The DMA channel has an interrupt event
DMA1IF	0	DMA Channel 1 Interrupt bit `0` No interrupt event `1` The DMA channel has an interrupt event

USBDMA1CUSB DMA Channel 1 Control Register

Address: 0xBF8E3204
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
DMABRSTM	10:9	DMA Burst Mode Selection bit `0` Burst Mode 0: Bursts of unspecified length `1` Burst Mode 1: INCR4 or unspecified length `2` Burst Mode 2: INCR8 `3` Burst Mode 3: INCR16
DMAERR	8	Bus Error bit `0` The software writes this to clear the error `1` A bus error has been observed on the input
DMAEP	7:4
DMAIE	3	DMA Interrupt Enable bit `0` Interrupt is disabled for this channel `1` Interrupt is enabled for this channel
DMAMODE	2	DMA Transfer Mode bit `0` DMA Mode0 Transfers `1` DMA Mode1 Transfers
DMADIR	1	DMA Transfer Direction bit `0` DMA Write (RX endpoint) `1` DMA Read (TX endpoint)
DMAEN	0	DMA Enable bit `0` Disable the DMA transfer `1` Enable the DMA transfer and start the transfer

USBDMA1AUSB DMA Channel 1 Memory Address Register

Address: 0xBF8E3208
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMAADDR	31:0

USBDMA1NUSB DMA Channel 1 Count Register

Address: 0xBF8E320C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMACOUNT	31:0

USBDMA2CUSB DMA Channel 2 Control Register

Address: 0xBF8E3214
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
DMABRSTM	10:9	DMA Burst Mode Selection bit `0` Burst Mode 0: Bursts of unspecified length `1` Burst Mode 1: INCR4 or unspecified length `2` Burst Mode 2: INCR8 `3` Burst Mode 3: INCR16
DMAERR	8	Bus Error bit `0` The software writes this to clear the error `1` A bus error has been observed on the input
DMAEP	7:4
DMAIE	3	DMA Interrupt Enable bit `0` Interrupt is disabled for this channel `1` Interrupt is enabled for this channel
DMAMODE	2	DMA Transfer Mode bit `0` DMA Mode0 Transfers `1` DMA Mode1 Transfers
DMADIR	1	DMA Transfer Direction bit `0` DMA Write (RX endpoint) `1` DMA Read (TX endpoint)
DMAEN	0	DMA Enable bit `0` Disable the DMA transfer `1` Enable the DMA transfer and start the transfer

USBDMA2AUSB DMA Channel 2 Memory Address Register

Address: 0xBF8E3218
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMAADDR	31:0

USBDMA2NUSB DMA Channel 2 Count Register

Address: 0xBF8E321C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMACOUNT	31:0

USBDMA3CUSB DMA Channel 3 Control Register

Address: 0xBF8E3224
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
DMABRSTM	10:9	DMA Burst Mode Selection bit `0` Burst Mode 0: Bursts of unspecified length `1` Burst Mode 1: INCR4 or unspecified length `2` Burst Mode 2: INCR8 `3` Burst Mode 3: INCR16
DMAERR	8	Bus Error bit `0` The software writes this to clear the error `1` A bus error has been observed on the input
DMAEP	7:4
DMAIE	3	DMA Interrupt Enable bit `0` Interrupt is disabled for this channel `1` Interrupt is enabled for this channel
DMAMODE	2	DMA Transfer Mode bit `0` DMA Mode0 Transfers `1` DMA Mode1 Transfers
DMADIR	1	DMA Transfer Direction bit `0` DMA Write (RX endpoint) `1` DMA Read (TX endpoint)
DMAEN	0	DMA Enable bit `0` Disable the DMA transfer `1` Enable the DMA transfer and start the transfer

USBDMA3AUSB DMA Channel 3 Memory Address Register

Address: 0xBF8E3228
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMAADDR	31:0

USBDMA3NUSB DMA Channel 3 Count Register

Address: 0xBF8E322C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMACOUNT	31:0

USBDMA4CUSB DMA Channel 4 Control Register

Address: 0xBF8E3234
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
DMABRSTM	10:9	DMA Burst Mode Selection bit `0` Burst Mode 0: Bursts of unspecified length `1` Burst Mode 1: INCR4 or unspecified length `2` Burst Mode 2: INCR8 `3` Burst Mode 3: INCR16
DMAERR	8	Bus Error bit `0` The software writes this to clear the error `1` A bus error has been observed on the input
DMAEP	7:4
DMAIE	3	DMA Interrupt Enable bit `0` Interrupt is disabled for this channel `1` Interrupt is enabled for this channel
DMAMODE	2	DMA Transfer Mode bit `0` DMA Mode0 Transfers `1` DMA Mode1 Transfers
DMADIR	1	DMA Transfer Direction bit `0` DMA Write (RX endpoint) `1` DMA Read (TX endpoint)
DMAEN	0	DMA Enable bit `0` Disable the DMA transfer `1` Enable the DMA transfer and start the transfer

USBDMA4AUSB DMA Channel 4 Memory Address Register

Address: 0xBF8E3238
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMAADDR	31:0

USBDMA4NUSB DMA Channel 4 Count Register

Address: 0xBF8E323C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMACOUNT	31:0

USBDMA5CUSB DMA Channel 5 Control Register

Address: 0xBF8E3244
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
DMABRSTM	10:9	DMA Burst Mode Selection bit `0` Burst Mode 0: Bursts of unspecified length `1` Burst Mode 1: INCR4 or unspecified length `2` Burst Mode 2: INCR8 `3` Burst Mode 3: INCR16
DMAERR	8	Bus Error bit `0` The software writes this to clear the error `1` A bus error has been observed on the input
DMAEP	7:4
DMAIE	3	DMA Interrupt Enable bit `0` Interrupt is disabled for this channel `1` Interrupt is enabled for this channel
DMAMODE	2	DMA Transfer Mode bit `0` DMA Mode0 Transfers `1` DMA Mode1 Transfers
DMADIR	1	DMA Transfer Direction bit `0` DMA Write (RX endpoint) `1` DMA Read (TX endpoint)
DMAEN	0	DMA Enable bit `0` Disable the DMA transfer `1` Enable the DMA transfer and start the transfer

USBDMA5AUSB DMA Channel 5 Memory Address Register

Address: 0xBF8E3248
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMAADDR	31:0

USBDMA5NUSB DMA Channel 5 Count Register

Address: 0xBF8E324C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMACOUNT	31:0

USBDMA6CUSB DMA Channel 6 Control Register

Address: 0xBF8E3254
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
DMABRSTM	10:9	DMA Burst Mode Selection bit `0` Burst Mode 0: Bursts of unspecified length `1` Burst Mode 1: INCR4 or unspecified length `2` Burst Mode 2: INCR8 `3` Burst Mode 3: INCR16
DMAERR	8	Bus Error bit `0` The software writes this to clear the error `1` A bus error has been observed on the input
DMAEP	7:4
DMAIE	3	DMA Interrupt Enable bit `0` Interrupt is disabled for this channel `1` Interrupt is enabled for this channel
DMAMODE	2	DMA Transfer Mode bit `0` DMA Mode0 Transfers `1` DMA Mode1 Transfers
DMADIR	1	DMA Transfer Direction bit `0` DMA Write (RX endpoint) `1` DMA Read (TX endpoint)
DMAEN	0	DMA Enable bit `0` Disable the DMA transfer `1` Enable the DMA transfer and start the transfer

USBDMA6AUSB DMA Channel 6 Memory Address Register

Address: 0xBF8E3258
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMAADDR	31:0

USBDMA6NUSB DMA Channel 6 Count Register

Address: 0xBF8E325C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMACOUNT	31:0

USBDMA7CUSB DMA Channel 7 Control Register

Address: 0xBF8E3264
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
DMABRSTM	10:9	DMA Burst Mode Selection bit `0` Burst Mode 0: Bursts of unspecified length `1` Burst Mode 1: INCR4 or unspecified length `2` Burst Mode 2: INCR8 `3` Burst Mode 3: INCR16
DMAERR	8	Bus Error bit `0` The software writes this to clear the error `1` A bus error has been observed on the input
DMAEP	7:4
DMAIE	3	DMA Interrupt Enable bit `0` Interrupt is disabled for this channel `1` Interrupt is enabled for this channel
DMAMODE	2	DMA Transfer Mode bit `0` DMA Mode0 Transfers `1` DMA Mode1 Transfers
DMADIR	1	DMA Transfer Direction bit `0` DMA Write (RX endpoint) `1` DMA Read (TX endpoint)
DMAEN	0	DMA Enable bit `0` Disable the DMA transfer `1` Enable the DMA transfer and start the transfer

USBDMA7AUSB DMA Channel 7 Memory Address Register

Address: 0xBF8E3268
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMAADDR	31:0

USBDMA7NUSB DMA Channel 7 Count Register

Address: 0xBF8E326C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMACOUNT	31:0

USBDMA8CUSB DMA Channel 8 Control Register

Address: 0xBF8E3274
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
DMABRSTM	10:9	DMA Burst Mode Selection bit `0` Burst Mode 0: Bursts of unspecified length `1` Burst Mode 1: INCR4 or unspecified length `2` Burst Mode 2: INCR8 `3` Burst Mode 3: INCR16
DMAERR	8	Bus Error bit `0` The software writes this to clear the error `1` A bus error has been observed on the input
DMAEP	7:4
DMAIE	3	DMA Interrupt Enable bit `0` Interrupt is disabled for this channel `1` Interrupt is enabled for this channel
DMAMODE	2	DMA Transfer Mode bit `0` DMA Mode0 Transfers `1` DMA Mode1 Transfers
DMADIR	1	DMA Transfer Direction bit `0` DMA Write (RX endpoint) `1` DMA Read (TX endpoint)
DMAEN	0	DMA Enable bit `0` Disable the DMA transfer `1` Enable the DMA transfer and start the transfer

USBDMA8AUSB DMA Channel 8 Memory Address Register

Address: 0xBF8E3278
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMAADDR	31:0

USBDMA8NUSB DMA Channel 8 Count Register

Address: 0xBF8E327C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMACOUNT	31:0

USBE1RPCUSB Endpoint 1 Request Packet Count Register (Host Mode Only)

Address: 0xBF8E3304
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
RQPKTCNT	15:0

USBE2RPCUSB Endpoint 2 Request Packet Count Register (Host Mode Only)

Address: 0xBF8E3308
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
RQPKTCNT	15:0

USBE3RPCUSB Endpoint 3 Request Packet Count Register (Host Mode Only)

Address: 0xBF8E330C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
RQPKTCNT	15:0

USBE4RPCUSB Endpoint 4 Request Packet Count Register (Host Mode Only)

Address: 0xBF8E3310
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
RQPKTCNT	15:0

USBE5RPCUSB Endpoint 5 Request Packet Count Register (Host Mode Only)

Address: 0xBF8E3314
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
RQPKTCNT	15:0

USBE6RPCUSB Endpoint 6 Request Packet Count Register (Host Mode Only)

Address: 0xBF8E3318
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
RQPKTCNT	15:0

USBE7RPCUSB Endpoint 7 Request Packet Count Register (Host Mode Only)

Address: 0xBF8E331C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
RQPKTCNT	15:0

USBDPBFDUSB Double Packet Buffer Disable Register

Address: 0xBF8E3340
Reset: 0x00000000
Access: read/write
Size: 32-bit

14 fields

Field	Bits	What it does
EP7TXD	23	TX Endpoint 7 Double Packet Buffer Disable bits `0` TX double packet buffering is enabled for endpoint x `1` TX double packet buffering is disabled for endpoint x
EP6TXD	22	TX Endpoint 6 Double Packet Buffer Disable bits `0` TX double packet buffering is enabled for endpoint x `1` TX double packet buffering is disabled for endpoint x
EP5TXD	21	TX Endpoint 5 Double Packet Buffer Disable bits `0` TX double packet buffering is enabled for endpoint x `1` TX double packet buffering is disabled for endpoint x
EP4TXD	20	TX Endpoint 4 Double Packet Buffer Disable bits `0` TX double packet buffering is enabled for endpoint x `1` TX double packet buffering is disabled for endpoint x
EP3TXD	19	TX Endpoint 3 Double Packet Buffer Disable bits `0` TX double packet buffering is enabled for endpoint x `1` TX double packet buffering is disabled for endpoint x
EP2TXD	18	TX Endpoint 2 Double Packet Buffer Disable bits `0` TX double packet buffering is enabled for endpoint x `1` TX double packet buffering is disabled for endpoint x
EP1TXD	17	TX Endpoint 1 Double Packet Buffer Disable bits `0` TX double packet buffering is enabled for endpoint x `1` TX double packet buffering is disabled for endpoint x
EP7RXD	7	RX Endpoint 7 Double Packet Buffer Disable bits `0` RX double packet buffering is enabled for endpoint x `1` RX double packet buffering is disabled for endpoint x
EP6RXD	6	RX Endpoint 6 Double Packet Buffer Disable bits `0` RX double packet buffering is enabled for endpoint x `1` RX double packet buffering is disabled for endpoint x
EP5RXD	5	RX Endpoint 5 Double Packet Buffer Disable bits `0` RX double packet buffering is enabled for endpoint x `1` RX double packet buffering is disabled for endpoint x
EP4RXD	4	RX Endpoint 4 Double Packet Buffer Disable bits `0` RX double packet buffering is enabled for endpoint x `1` RX double packet buffering is disabled for endpoint x
EP3RXD	3	RX Endpoint 3 Double Packet Buffer Disable bits `0` RX double packet buffering is enabled for endpoint x `1` RX double packet buffering is disabled for endpoint x
EP2RXD	2	RX Endpoint 2 Double Packet Buffer Disable bits `0` RX double packet buffering is enabled for endpoint x `1` RX double packet buffering is disabled for endpoint x
EP1RXD	1	RX Endpoint 1 Double Packet Buffer Disable bits `0` RX double packet buffering is enabled for endpoint x `1` RX double packet buffering is disabled for endpoint x

USBTMCON1USB Timing Control Register 1

Address: 0xBF8E3344
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
TUCH	15:0
THHSRTN	31:16

USBTMCON2USB Timing Control Register 2

Address: 0xBF8E3348
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
THSBT	3:0

USBLPMR1USB Link Power Management Control Register 1

Address: 0xBF8E3360
Reset: 0x00000000
Access: read/write
Size: 32-bit

14 fields

Field	Bits	What it does
LPMERRIE	29	LPM Error Interrupt Enable bit `0` LPMERR interrupt is disabled `1` LPMERR interrupt is enabled
LPMRESIE	28	LPM Resume Interrupt Enable bit `0` LPMRES interrupt is disabled `1` LPMRES interrupt is enabled
LPMACKIE	27	LPM Acknowledge Interrupt Enable bit `0` Disable the LPMACK Interrupt `1` Enable the LPMACK Interrupt
LPMNYIE	26	LPM NYET Interrupt Enable bit `0` Disable the LPMNYET Interrupt `1` Enable the LPMNYET Interrupt
LPMSTIE	25	LPM STALL Interrupt Enable bit `0` Disable the LPMST Interrupt `1` Enable the LPMST Interrupt
LPMTOIE	24	LPM Time-out Interrupt Enable bit `0` Disable the LPMTO Interrupt `1` Enable the LPMTO Interrupt
LPMNAK	20	LPM-only Transaction Setting bit `0` Normal transaction operation `1` All endpoints will respond to all transactions other than a LPM transaction with a NAK
LPMEN	19:18	LPM Enable bits ( `0` LPM Extended transactions are supported `1` LPM mode is not supported but Extended transactions are supported `2` LPM and Extended transactions are not supported `3` LPM Extended transactions are supported
LPMRES	17	LPM Resume bit `0` No resume operation `1` Initiate resume (remote wake-up). Resume signaling is asserted for 50 s.
LPMXMT	16	LPM Transition to the L1 State bit `0` (Device and host modes) Maintain current state `1` (Device mode) USB module will transition to the L1 state upon the receipt of the next LPM transaction. LPMEN must be set to 0b11. Both LPMXMT and LPMEN must be set in the same cycle. / (Host mode)USB module will transmit an LPM transaction. This bit is self clearing
ENDPOINT	15:12
RMTWAK	8	Remote Wake-up Enable bit `0` Remote wake-up is disabled `1` Remote wake-up is enabled
HIRD	7:4
LNKSTATE	3:0

USBLPMR2USB Link Power Management Control Register 2

Address: 0xBF8E3364
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
LPMFADDR	14:8
LPMERR	5
LPMRES	4
LPMNC	3
LPMACK	2
LPMNY	1
LPMST	0