PIC32MZ1025DAR169 DDR registers The 63 registers of DDR (DDR2 memory controller), from 0xBF8E8000, with their reset value and every field. The PIC32MZ1025DAR169 has 2308 registers in 102 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
DDR DDR2 memory controller DDRTSELDDR Target Select Register
Address 0xBF8E8000
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does TSEL 7:0
DDRMINLIMDDR Minimum Burst Limit Register
Address 0xBF8E8004
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does TSEL 4:0
DDRRQPERDDR Request Period Register
Address 0xBF8E8008
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RQPER 7:0
DDRMINCMDDDR Minimum Command Register
Address 0xBF8E800C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does MINCMD 7:0
DDRMEMCONDDR Memory Control Register
Address 0xBF8E8010
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does INITDN 1 Memory Initialize Done bit0 Controller not enabled for regular operation1 All commands have been issued; the controller is enabled for regular operation STINIT 0 Memory Initialize Start bit0 Do not start memory initialization1 Start memory initialization
DDRMEMCFG0DDR Memory Configuration Register 0
Address 0xBF8E8014
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does APCHRGEN 30 Automatic Precharge Enable bit0 Do not issue an auto-precharged command1 Issue an auto-precharged command CLHADDR 28:24 CSADDR 20:16 BNKADDR 12:8 RWADDR 4:0
DDRMEMCFG1DDR Memory Configuration Register 1
Address 0xBF8E8018
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does RWADDRMSK 12:0
DDRMEMCFG2DDR Memory Configuration Register 2
Address 0xBF8E801C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CLADDRHMSK 12:0
DDRMEMCFG3DDR Memory Configuration Register 3
Address 0xBF8E8020
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CLADDRLMSK 12:0
DDRMEMCFG4DDR Memory Configuration Register 4
Address 0xBF8E8024
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSADDRMSK 12:8 BNKADDRMSK 4:0
DDRREFCFGDDR Refresh Configuration Register
Address 0xBF8E8028
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does MAXREFS 26:24 REFDLY 23:16 REFCNT 15:0
DDRPWRCFGDDR Power Configuration Register
Address 0xBF8E802C
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does PCHRGPWRDN 22 Precharge Power Down Only bit0 Do not allow automatic entry into Precharge Power Down mode.1 Allow automatic entry into Precharge Power Down mode. SLFREFDLY 21:12 Self Refresh Delay bits1 1024 clocks511 2111452 clocks PWRDNDLY 11:4 Refresh Count bits1 4 clocks255 1020 clocks ASLFREFEN 3 Automatic Self Refresh Enable bit0 Do not allow automatic entry into Self Refresh mode.1 Allow automatic entry into Self Refresh mode. APWRDNEN 2 Automatic Power Down Enable bit0 Do not allow automatic entry into Power Down mode.1 Allow automatic entry into Power Down mode.
DDRDLYCFG0DDR Delay Configuration Register 0
Address 0xBF8E8030
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does R2WDLY 27:24 W2WCSDLY 23:20 W2WDLY 19:16 R2RCSDLY 15:12 R2RDLY 11:8 W2RCSDLY 7:4 W2RDLY 3:0 RMWDLY 31:28
DDRDLYCFG1DDR Delay Configuration Register 1
Address 0xBF8E8034
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does SLFREFEXDLY8 30 NXTDATAVDLY4 29 W2RCSDLY4 28 W2RDLY4 27 W2PCHRGDLY4 26 PWRDNEXDLY 25:20 PWRDNMINDLY 19:16 SLFREFEXDLY 15:8 SLFREFMINDLY 7:0
DDRDLYCFG2DDR Delay Configuration Register 2
Address 0xBF8E8038
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does PCHRG2RASDLY 27:24 RAS2CASDLY 23:20 RAS2RASDLY 19:16 W2PCHRGDLY 15:12 R2PCHRGDLY 11:8 PCHRGALLDLY 3:0 RBENDDLY 31:28
DDRODTCFGDDR On-Die Termination Configuration Register
Address 0xBF8E8040
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does ODTWLEN 22:20 ODTRLEN 18:16 ODTWDLY 15:12 ODTRDLY 11:8 ODTCSEN 7:0
DDRXFERCFGDDR Transfer Configuration Register
Address 0xBF8E8044
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does MAXBURST 27:24 RDATENDLY 19:16 NXTDATAVDLY 7:4 NXTDATRQDLY 3:0 BIGENDIAN 31 Big Endian bit0 Data is little endian format1 Data is big endian format
DDRCMDISSUEDDR Command Issue Register
Address 0xBF8E8048
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does NXTDATAVDLY 4 NUMHOSTCMDS 3:0
DDRODTENCFGDDR On-Die Termination Enable Configuration Register
Address 0xBF8E804C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does ODTWEN 16 On-Die Termination Write Enable bit0 The Chip Select represented by the OTDCSEN bits (DDRODTCFG<7:0>) has ODT disabled for data reads1 The Chip Select represented by the OTDCSEN bits (DDRODTCFG<7:0>) has ODT enabled for data reads ODTREN 0 On-Die Termination Read Enable bit0 The Chip Select represented by the OTDCSEN bits (DDRODTCFG<7:0>) has ODT disabled for data writes1 The Chip Select represented by the OTDCSEN bits (DDRODTCFG<7:0>) has ODT enabled for data writes
DDRMEMWIDTHDDR Memory Width Register
Address 0xBF8E8050
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does HALFRATE 3 Half-rate Mode bit0 Full-rate mode1 Half-rate mode
DDRCMD10DDR Host Command 1 Register x (x = 0 through 15)
Address 0xBF8E8080
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does WENCMD2 23 CASCMD2 22 RASCMD2 21 CSCMD2 20:13 CLKENCMD2 12 WENCMD1 11 CASCMD1 10 RASCMD1 9 CSCMD1 8:1 CLKENCMD1 0 MDALCMD 31:24
DDRCMD11DDR Host Command 1 Register x (x = 0 through 15)
Address 0xBF8E8084
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does WENCMD2 23 CASCMD2 22 RASCMD2 21 CSCMD2 20:13 CLKENCMD2 12 WENCMD1 11 CASCMD1 10 RASCMD1 9 CSCMD1 8:1 CLKENCMD1 0 MDALCMD 31:24
DDRCMD12DDR Host Command 1 Register x (x = 0 through 15)
Address 0xBF8E8088
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does WENCMD2 23 CASCMD2 22 RASCMD2 21 CSCMD2 20:13 CLKENCMD2 12 WENCMD1 11 CASCMD1 10 RASCMD1 9 CSCMD1 8:1 CLKENCMD1 0 MDALCMD 31:24
DDRCMD13DDR Host Command 1 Register x (x = 0 through 15)
Address 0xBF8E808C
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does WENCMD2 23 CASCMD2 22 RASCMD2 21 CSCMD2 20:13 CLKENCMD2 12 WENCMD1 11 CASCMD1 10 RASCMD1 9 CSCMD1 8:1 CLKENCMD1 0 MDALCMD 31:24
DDRCMD14DDR Host Command 1 Register x (x = 0 through 15)
Address 0xBF8E8090
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does WENCMD2 23 CASCMD2 22 RASCMD2 21 CSCMD2 20:13 CLKENCMD2 12 WENCMD1 11 CASCMD1 10 RASCMD1 9 CSCMD1 8:1 CLKENCMD1 0 MDALCMD 31:24
DDRCMD15DDR Host Command 1 Register x (x = 0 through 15)
Address 0xBF8E8094
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does WENCMD2 23 CASCMD2 22 RASCMD2 21 CSCMD2 20:13 CLKENCMD2 12 WENCMD1 11 CASCMD1 10 RASCMD1 9 CSCMD1 8:1 CLKENCMD1 0 MDALCMD 31:24
DDRCMD16DDR Host Command 1 Register x (x = 0 through 15)
Address 0xBF8E8098
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does WENCMD2 23 CASCMD2 22 RASCMD2 21 CSCMD2 20:13 CLKENCMD2 12 WENCMD1 11 CASCMD1 10 RASCMD1 9 CSCMD1 8:1 CLKENCMD1 0 MDALCMD 31:24
DDRCMD17DDR Host Command 1 Register x (x = 0 through 15)
Address 0xBF8E809C
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does WENCMD2 23 CASCMD2 22 RASCMD2 21 CSCMD2 20:13 CLKENCMD2 12 WENCMD1 11 CASCMD1 10 RASCMD1 9 CSCMD1 8:1 CLKENCMD1 0 MDALCMD 31:24
DDRCMD18DDR Host Command 1 Register x (x = 0 through 15)
Address 0xBF8E80A0
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does WENCMD2 23 CASCMD2 22 RASCMD2 21 CSCMD2 20:13 CLKENCMD2 12 WENCMD1 11 CASCMD1 10 RASCMD1 9 CSCMD1 8:1 CLKENCMD1 0 MDALCMD 31:24
DDRCMD19DDR Host Command 1 Register x (x = 0 through 15)
Address 0xBF8E80A4
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does WENCMD2 23 CASCMD2 22 RASCMD2 21 CSCMD2 20:13 CLKENCMD2 12 WENCMD1 11 CASCMD1 10 RASCMD1 9 CSCMD1 8:1 CLKENCMD1 0 MDALCMD 31:24
DDRCMD110DDR Host Command 1 Register x (x = 0 through 15)
Address 0xBF8E80A8
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does WENCMD2 23 CASCMD2 22 RASCMD2 21 CSCMD2 20:13 CLKENCMD2 12 WENCMD1 11 CASCMD1 10 RASCMD1 9 CSCMD1 8:1 CLKENCMD1 0 MDALCMD 31:24
DDRCMD111DDR Host Command 1 Register x (x = 0 through 15)
Address 0xBF8E80AC
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does WENCMD2 23 CASCMD2 22 RASCMD2 21 CSCMD2 20:13 CLKENCMD2 12 WENCMD1 11 CASCMD1 10 RASCMD1 9 CSCMD1 8:1 CLKENCMD1 0 MDALCMD 31:24
DDRCMD112DDR Host Command 1 Register x (x = 0 through 15)
Address 0xBF8E80B0
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does WENCMD2 23 CASCMD2 22 RASCMD2 21 CSCMD2 20:13 CLKENCMD2 12 WENCMD1 11 CASCMD1 10 RASCMD1 9 CSCMD1 8:1 CLKENCMD1 0 MDALCMD 31:24
DDRCMD113DDR Host Command 1 Register x (x = 0 through 15)
Address 0xBF8E80B4
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does WENCMD2 23 CASCMD2 22 RASCMD2 21 CSCMD2 20:13 CLKENCMD2 12 WENCMD1 11 CASCMD1 10 RASCMD1 9 CSCMD1 8:1 CLKENCMD1 0 MDALCMD 31:24
DDRCMD114DDR Host Command 1 Register x (x = 0 through 15)
Address 0xBF8E80B8
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does WENCMD2 23 CASCMD2 22 RASCMD2 21 CSCMD2 20:13 CLKENCMD2 12 WENCMD1 11 CASCMD1 10 RASCMD1 9 CSCMD1 8:1 CLKENCMD1 0 MDALCMD 31:24
DDRCMD115DDR Host Command 1 Register x (x = 0 through 15)
Address 0xBF8E80BC
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does WENCMD2 23 CASCMD2 22 RASCMD2 21 CSCMD2 20:13 CLKENCMD2 12 WENCMD1 11 CASCMD1 10 RASCMD1 9 CSCMD1 8:1 CLKENCMD1 0 MDALCMD 31:24
DDRCMD20DDR Host Command 2 Register x (x = 0 through 15)
Address 0xBF8E80C0
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does WAIT 19:11 BNKADDRCMD 10:8 MDADDRHCMD 7:0
DDRCMD21DDR Host Command 2 Register x (x = 0 through 15)
Address 0xBF8E80C4
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does WAIT 19:11 BNKADDRCMD 10:8 MDADDRHCMD 7:0
DDRCMD22DDR Host Command 2 Register x (x = 0 through 15)
Address 0xBF8E80C8
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does WAIT 19:11 BNKADDRCMD 10:8 MDADDRHCMD 7:0
DDRCMD23DDR Host Command 2 Register x (x = 0 through 15)
Address 0xBF8E80CC
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does WAIT 19:11 BNKADDRCMD 10:8 MDADDRHCMD 7:0
DDRCMD24DDR Host Command 2 Register x (x = 0 through 15)
Address 0xBF8E80D0
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does WAIT 19:11 BNKADDRCMD 10:8 MDADDRHCMD 7:0
DDRCMD25DDR Host Command 2 Register x (x = 0 through 15)
Address 0xBF8E80D4
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does WAIT 19:11 BNKADDRCMD 10:8 MDADDRHCMD 7:0
DDRCMD26DDR Host Command 2 Register x (x = 0 through 15)
Address 0xBF8E80D8
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does WAIT 19:11 BNKADDRCMD 10:8 MDADDRHCMD 7:0
DDRCMD27DDR Host Command 2 Register x (x = 0 through 15)
Address 0xBF8E80DC
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does WAIT 19:11 BNKADDRCMD 10:8 MDADDRHCMD 7:0
DDRCMD28DDR Host Command 2 Register x (x = 0 through 15)
Address 0xBF8E80E0
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does WAIT 19:11 BNKADDRCMD 10:8 MDADDRHCMD 7:0
DDRCMD29DDR Host Command 2 Register x (x = 0 through 15)
Address 0xBF8E80E4
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does WAIT 19:11 BNKADDRCMD 10:8 MDADDRHCMD 7:0
DDRCMD210DDR Host Command 2 Register x (x = 0 through 15)
Address 0xBF8E80E8
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does WAIT 19:11 BNKADDRCMD 10:8 MDADDRHCMD 7:0
DDRCMD211DDR Host Command 2 Register x (x = 0 through 15)
Address 0xBF8E80EC
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does WAIT 19:11 BNKADDRCMD 10:8 MDADDRHCMD 7:0
DDRCMD212DDR Host Command 2 Register x (x = 0 through 15)
Address 0xBF8E80F0
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does WAIT 19:11 BNKADDRCMD 10:8 MDADDRHCMD 7:0
DDRCMD213DDR Host Command 2 Register x (x = 0 through 15)
Address 0xBF8E80F4
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does WAIT 19:11 BNKADDRCMD 10:8 MDADDRHCMD 7:0
DDRCMD214DDR Host Command 2 Register x (x = 0 through 15)
Address 0xBF8E80F8
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does WAIT 19:11 BNKADDRCMD 10:8 MDADDRHCMD 7:0
DDRCMD215DDR Host Command 2 Register x (x = 0 through 15)
Address 0xBF8E80FC
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does WAIT 19:11 BNKADDRCMD 10:8 MDADDRHCMD 7:0
DDRSCLSTARTDDL SELF CALIBRATION LOGIC START REGISTER
Address 0xBF8E9100
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does SCLPHCAL 29 SCLSTART 28 Start Self Calibration Logic bit0 Do not start self calibration1 Start self calibration SCLEN 26 Self Calibration Logic Enable bit0 Disable dynamic self calibration logic1 Enable dynamic self calibration logic SCULBPASS 1 SCLLBPASS 0 Self Calibration Logic Lower Data Byte Status bit0 Self calibration logic for lower data byte failed1 Self calibration logic for lower data byte passed
DDRSCLLATDDL Self Calibration Logic Latency Register
Address 0xBF8E910C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does DDRCLKDLY 7:4 CAPCLKDLY 3:0
DDRSCLCFG0DDR SCL Configuration Register 0
Address 0xBF8E9118
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does ODTCSW 24 On-Die Termination Chip Select Write bit0 ODT is turned off to the DRAM on CS0 during writes performed by the SCL.1 ODT is turned on to the DRAM on CS0 during writes performed by the SCL RCASLAT 7:4 DDR2 1 DDR2 bit0 DDR2 is not connected1 DDR2 is connected BURST8 0 PHY Burst 8 bit0 DRAM is in burst 4 mode while running SCL test1 DRAM is in burst 8 mode while running SCL test
DDRSCLCFG1DDR SCL Configuration Register 1
Address 0xBF8E911C
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does DBLREFDLY 12 Double Reference Delay bit0 SCL operation delay not doubled1 SCL operation delay doubled WCASLAT 11:8 SCLCSEN 0 SCL Chip Select Enable bit0 Do not run SCL on Chip Select 01 Run SCL on Chip Select 0
DDRPHYPADCONDDR PHY Pad Control Register
Address 0xBF8E9120
Reset 0x00000000
Access read/write
Size 32-bit 14 fields
Field Bits What it does PREAMBDLY 30:29 Preamble Delay bits0 2 cycle preamble1 1.5 cycle preamble2 1 cycle preamble3 Reserved RCVREN 28 Receiver Enable bit0 Pad receivers on bidirectional I/Os are turned off1 Pad receivers on bidirectional I/Os are turned on DRVSTRPFET 23:20 PFET Drive Strength bits0 Minimum drive strength.15 Maximum drive strength DRVSTRNFET 19:16 NFET Drive Strength bits0 Minimum drive strength.15 Maximum drive strength HALFRATE 14 Half Rate bit0 Controller clock is running at full rate with respect to PHY1 Controller clock is running at half rate with respect to PHY WRCMDDLY 13 Write Command Delay bit0 No Write command delay1 Write command delay NOEXTDLL 9 No External DLL bit0 Use external DLL.1 Use internal digital DLL. EOENCLKCYC 8 Extra Output Enable bit0 Do not drive pad output enables for an extra clock cycle after a write burst1 Drive pad output enables for an extra clock cycle after a write burst ODTPUCAL 7:6 On-Die Termination Pull-up Calibration bits0 Minimum ODT impedance3 Maximum ODT impedance ODTPDCAL 5:4 ADDCDRVSEL 3 Address and Control Pads Drive Strength Select bit0 60% Drive Strength1 Full drive strength DATDRVSEL 2 Data Pad Drive Strength Select bit0 60% Drive Strength1 Full Drive Strength SCLCSEN 1 SCLCSEN 0
DDRPHYDLLRDDR PHY DLL Recalibrate Register
Address 0xBF8E9124
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does DISRECALIB 26 Disable Recalibration bit0 Recalibrate the digital DLL in accordance with the value of the RECALIBCNT bits1 Do not recalibrate the digital DLL after the first time RECALIBCNT 25:8 DLYSTVAL 31:28
DDRPHYDLLCTRLDDR Phy Trim Register
Address 0xBF8E9128
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DDRDLLTRIM 7:0 Trim Setting bits
DDRPHYCLKDLYDDR Clock Delta Delay Register
Address 0xBF8E9140
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does SCLUBPASS 5 Self Calibration Logic Upper Data Byte Status bit0 Self calibration logic for upper data byte is failed2 Self calibration logic for upper data byte is passed SCLLBPASS 4 Self Calibration Logic Lower Data Byte Status bit0 Self calibration logic for lower data byte is failed2 Self calibration logic for lower data byte is passed CLKDLYDELTA 2:0 DDR Clock Delay Delta bits0 0 DDR clocks1 1 DDR clocks2 2 DDR clocks3 3 DDR clocks4 4 DDR clocks5 5 DDR clocks6 6 DDR clocks7 7 DDR clocks
DDRADLLBYPDDR Analog DLL Bypass Register
Address 0xBF8E915C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does ANLDLLBYP 24 Bypass Analog DLL bit0 Reserved; do not use1 Bypass the Analog DLL and use the PHY Digital DLL
DDRSCLCFG2DDR Analog DLL Bypass Register
Address 0xBF8E916C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SCLLANSEL 1:0 DDR SCL Configuration Register 20 Use both lanes1 Use the lower byte lane2 Use the upper byte lane3 Reserved; do not use
DDRPHYSCLADRDDR PHY SCL Address Register
Address 0xBF8E9188
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does SCLCOLADR 28:16 SCL Column Address bits SCLROWADR 15:0 SCL Row Address bits SCLBANKADR 31:29 SCL Bank Address bits
BETA