The 6 registers of DMAC (DMA controller), from 0xBF811000, with their reset value and every field. The PIC32MZ1025W104132 has 1091 registers in 66 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
DMAC DMA controller
DMACONDMA Controller Control Register
Address
0xBF811000
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
ON
15
DMA On bit
0 DMA module is enabled
0 DMA module is disabled
SUSPEND
12
DMA Suspend bit
0 DMA operates normally
1 DMA transfers are suspended to allow CPU uninterrupted access to data bus
DMABUSY
11
DMA Module Busy bit
0 DMA module is disabled and not actively transferring data
1 DMA module is active and is transferring data
DMASTATDMA Status Register
Address
0xBF811010
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
DMACH
2:0
RDWR
31
Read/Write Status bit
0 Last DMA bus access when an error was detected was a write
1 Last DMA bus access when an error was detected was a read
DMAADDRDMA Address Register
Address
0xBF811020
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
DMAADDR
31:0
DCRCCONDMA CRC Control Register
Address
0xBF811030
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
BYTO
29:28
CRC Byte Order Selection bits
0 No swapping (i.e.
1 Endian byte swap on word boundaries (i.e.
2 Swap half-words on word boundaries (i.e.
3 Endian byte swap on half-word boundaries (i.e.
WBO
27
CRC Write Byte Order Selection bit
0 Source data is written to the destination unaltered
1 Source data is written to the destination re-ordered as defined by BYTO
BITO
24
CRC Bit Order Selection bit
0 (When CRCTYP (i.e.
1 (When CRCTYP (ie
PLEN
12:8
Polynomial Length bits
1 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 0
2 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 1
3 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 2
4 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 3
5 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 4
6 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 5
7 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 6
8 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 7
9 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 8
10 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 9
11 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 10
12 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 11
13 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 12
14 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 13
15 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 14
16 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 15
17 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 16
18 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 17
19 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 18
20 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 19
21 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 20
22 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 21
23 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 22
24 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 23
25 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 24
26 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 25
27 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 26
28 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 27
29 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 28
30 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 29
31 (CRC module is in IP Header mode)These bits are unused. / (CRC module is in LFSR mode) Denotes polynomial length of 30
CRCEN
7
CRC Enable bit
0 CRC module is disabled and channel transfers proceed normally
1 CRC module is enabled and channel transfers are routed through the CRC module
CRCAPP
6
CRC Append Mode bit
0 The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the destination
1 The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer completes the DMA writes the calculated CRC value to the location given by CHxDSA
CRCTYP
5
CRC Type Selection bit
0 The CRC module will calculate a LFSR CRC
1 The CRC module will calculate an IP header checksum
CRCCH
2:0
CRC Channel Select bits
0 CRC is assigned to Channel 0
1 CRC is assigned to Channel 1
2 CRC is assigned to Channel 2
3 CRC is assigned to Channel 3
4 CRC is assigned to Channel 4
5 CRC is assigned to Channel 5
6 CRC is assigned to Channel 6
7 CRC is assigned to Channel 7
DCRCDATADMA CRC Data Register
Address
0xBF811040
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DCRCDATA
31:0
CRC Data Register bits
-1 (CRC module is in IP Header mode) Only the lower 16 bits contain IP header checksum information. Seed with ffffffff / (CRC module is in LFSR mode) Seed with ffffffff
0 (CRC module is in IP Header mode) Only the lower 16 bits contain IP header checksum information. Seed with 0 / (CRC module is in LFSR mode) Seed with 0
1 (CRC module is in IP Header mode) Only the lower 16 bits contain IP header checksum information. Seed with 1 / (CRC module is in LFSR mode) Seed with 1
BETA