The 13 registers of PORTC (I/O port C), from 0xBF820210, with their reset value and every field. The PIC32MZ1025W104132 has 1091 registers in 66 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
PORTC I/O port C
TRISC
Address
0xBF820210
Reset
0x0000FFFF
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
TRISC15
15
TRISC14
14
TRISC13
13
TRISC12
12
TRISC11
11
TRISC10
10
TRISC9
9
TRISC8
8
TRISC7
7
TRISC6
6
TRISC5
5
TRISC4
4
TRISC3
3
TRISC2
2
TRISC1
1
TRISC0
0
PORTC
Address
0xBF820220
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
RC15
15
RC14
14
RC13
13
RC12
12
RC11
11
RC10
10
RC9
9
RC8
8
RC7
7
RC6
6
RC5
5
RC4
4
RC3
3
RC2
2
RC1
1
RC0
0
LATC
Address
0xBF820230
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
LATC15
15
LATC14
14
LATC13
13
LATC12
12
LATC11
11
LATC10
10
LATC9
9
LATC8
8
LATC7
7
LATC6
6
LATC5
5
LATC4
4
LATC3
3
LATC2
2
LATC1
1
LATC0
0
ODCC
Address
0xBF820240
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
ODCC15
15
ODCC14
14
ODCC13
13
ODCC12
12
ODCC11
11
ODCC10
10
ODCC9
9
ODCC8
8
ODCC7
7
ODCC6
6
ODCC5
5
ODCC4
4
ODCC3
3
ODCC2
2
ODCC1
1
ODCC0
0
CNPUC
Address
0xBF820250
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
CNPUC15
15
CNPUC14
14
CNPUC13
13
CNPUC12
12
CNPUC11
11
CNPUC10
10
CNPUC9
9
CNPUC8
8
CNPUC7
7
CNPUC6
6
CNPUC5
5
CNPUC4
4
CNPUC3
3
CNPUC2
2
CNPUC1
1
CNPUC0
0
CNPDC
Address
0xBF820260
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
CNPDC15
15
CNPDC14
14
CNPDC13
13
CNPDC12
12
CNPDC11
11
CNPDC10
10
CNPDC9
9
CNPDC8
8
CNPDC7
7
CNPDC6
6
CNPDC5
5
CNPDC4
4
CNPDC3
3
CNPDC2
2
CNPDC1
1
CNPDC0
0
CNCONCChange Notice control for PORTx Register
Address
0xBF820270
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
ON
15
Change Notice Control ON bit
0 CN is disabled
1 CN is enabled
SIDL
13
EDGEDETECT
11
Change Notification Style bit
0 Mismatch Style. Detect change from last PORTx read (CNSTATx used for CN Event).
1 Edge Style. Detect edge transitions (CNFx used for CN Event).
BETA