PIC32MZ1064DAA169 UART2 registers

The 5 registers of UART2 (UART 2), from 0xBF822200, with their reset value and every field. The PIC32MZ1064DAA169 has 2244 registers in 101 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

UART2 UART 2

U2MODEUARTx Mode Register

Address
0xBF822200
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
FieldBitsWhat it does
SLPEN23Run During Sleep Enable bit
  • 0 UARTx BRG clock is turned off during Sleep mode
  • 1 UARTx BRG clock runs during Sleep mode
ACTIVE22UARTx Module Running Status bit
  • 0 UARTx module is not active (UxMODE register can be updated)
  • 1 UARTx module is active (UxMODE register should not be updated)
CLKSEL18:17UARTx Module Clock Selection bits
  • 0 BRG clock is PBCLK2 (turned off in Sleep mode)
  • 1 BRG clock is SYSCLK (turned off in Sleep mode)
  • 2 BRG clock is FRC
  • 3 BRG clock is PBCLK2
OVFDIS16
ON15UARTx Enable bit
  • 0 UARTx module is disabled. All UARTx pins are controlled by corresponding bits in the PORTx
  • 1 UARTx module is enabled. UARTx pins are controlled by UARTx as defined by UEN and UTXEN control bits
SIDL13Stop in Idle Mode bit
  • 0 Continue operation in Idle mode
  • 1 Discontinue operation when device enters Idle mode
IREN12IrDA Encoder and Decoder Enable bit
  • 0 IrDA is disabled
  • 1 IrDA is enabled
RTSMD11Mode Selection for UxRTS Pin bit
  • 0 UxRTS pin is in Flow Control mode
  • 1 UxRTS pin is in Simplex mode
UEN9:8UARTx Module Enable bits
  • 0 UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by corresponding bits in the PORTx register
  • 1 UxTX
  • 2 UxTX
  • 3 UxTX
WAKE7Enable Wake-up on Start bit Detect During Sleep Mode bit
  • 0 Wake-up disabled
  • 1 Wake-up enabled
LPBACK6UARTx Loopback Mode Select bit
  • 0 Loopback mode is disabled
  • 1 Loopback mode is enabled
ABAUD5Auto-Baud Enable bit
  • 0 Baud rate measurement disabled or completed
  • 1 Enable baud rate measurement on the next character requires reception of Sync character (0x55); cleared by hardware upon completion
RXINV4Receive Polarity Inversion bit
  • 0 UxRX Idle state is 1
  • 1 UxRX Idle state is 0
BRGH3High Baud Rate Enable bit
  • 0 Standard Speed mode 16x baud clock enabled
  • 1 High-Speed mode 4x baud clock enabled
PDSEL2:1Parity and Data Selection bits
  • 0 8-bit data, no parity
  • 1 8-bit data, even parity
  • 2 8-bit data, odd parity
  • 3 9-bit data, no parity
STSEL0Stop Selection bit
  • 0 1 Stop bit
  • 1 2 Stop bits

U2STAUARTx Status and Control Register

Address
0xBF822210
Reset
0x00000110
Access
read/write
Size
32-bit
16 fields
FieldBitsWhat it does
ADDR23:16
UTXISEL15:14TX Interrupt Mode Selection bits
  • 0 Interrupt is generated and asserted while the transmit buffer contains at least one empty space
  • 1 Interrupt is generated and asserted when all characters have been transmitted
  • 2 Interrupt is generated and asserted while the transmit buffer is empty
  • 3 Reserved
UTXINV13Transmit Polarity Inversion bit
  • 0 (If IrDA mode is disabled) UxTX Idle state is 1 / (If IrDA mode is enabled) IrDA encoded UxTX Idle state is 0
  • 1 (If IrDA mode is disabled) UxTX Idle state is 0 / (If IrDA mode is enabled) IrDA encoded UxTX Idle state is 1
URXEN12Receiver Enable bit
  • 0 UARTx receiver is disabled. UxRX pin is ignored by the UARTx module
  • 1 UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1)
UTXBRK11Transmit Break bit
  • 0 Break transmission is disabled or completed
  • 1 Send Break on next transmission. Start bit followed by twelve 0 bits
UTXEN10Transmit Enable bit
  • 0 UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset
  • 1 UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1)
UTXBF9Transmit Buffer Full Status bit (read-only)
  • 0 Transmit buffer is not full
  • 1 Transmit buffer is full
TRMT8Transmit Shift Register is Empty bit (read-only)
  • 0 Transmit shift register is not empty
  • 1 Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)
URXISEL7:6Receive Interrupt Mode Selection bit
  • 0 Interrupt flag bit is asserted while receive buffer is not empty (i.e.
  • 1 Interrupt flag bit is asserted while receive buffer is 1/2 or more full
  • 2 Interrupt flag bit is asserted while receive buffer is 3/4 or more full
  • 3 Reserved
ADDEN5Address Character Detect bit (bit 8 of received data = 1)
  • 0 Address Detect mode is disabled
  • 1 Address Detect mode is enabled. If 9-bit mode is not selected
RIDLE4Receiver Idle bit (read-only)
  • 0 Data is being received
  • 1 Receiver is Idle
PERR3Parity Error Status bit (read-only)
  • 0 Parity error has not been detected
  • 1 Parity error has been detected for the current character
FERR2Framing Error Status bit (read-only)
  • 0 Framing error has not been detected
  • 1 Framing error has been detected for the current character
OERR1Receive Buffer Overrun Error Status bit.
  • 0 Receive buffer has not overflowed
  • 1 Receive buffer has overflowed
URXDA0Receive Buffer Data Available bit (read-only)
  • 0 Receive buffer is empty
  • 1 Receive buffer has data
MASK31:24UARTx Address Match Mask bits
  • 0 Corresponding ADDRx bits are not used to detect the address match.
  • 510 Corresponding ADDRx bits are used to detect the address match

U2TXREG

Address
0xBF822220
Reset
0x00000000
Access
read/write
Size
32-bit

U2RXREG

Address
0xBF822230
Reset
0x00000000
Access
read only
Size
32-bit

U2BRG

Address
0xBF822240
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
BRG19:0