The 26 registers of SQI (Serial quad interface), from 0xBF8E2000, with their reset value and every field. The PIC32MZ1064DAB169 has 2254 registers in 102 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
SQI Serial quad interface
SQI1XCON1SQI XIP Control Register 1
Address
0xBF8E2000
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
SDRCMD
29
SQI Command in SDR Mode bit
0 SQI command is in DDR mode and SQI data is in DDR mode
1 SQI command is in SDR mode and SQI data is in DDR mode
DDRDATA
28
SQI Data DDR Mode bit
0 SQI data bytes are transferred in SDR mode
1 SQI data bytes are transferred in DDR mode
DDRDUMMY
27
SQI Dummy DDR Mode bit
0 SQI dummy bytes are transferred in SDR mode
1 SQI dummy bytes are transferred in DDR mode
DDRMODE
26
SQI DDR Mode bit
0 SQI mode bytes are transferred in SDR mode
1 SQI mode bytes are transferred in DDR mode
DDRADDR
25
SQI Address Mode bit
0 SQI address bytes are transferred in SDR mode
1 SQI address bytes are transferred in DDR mode
DDRCMD
24
SQI DDR Command Mode bit
0 SQI command bytes are transferred in SDR mode
1 SQI command bytes are transferred in DDR mode
DUMMYBYTES
23:21
Transmit Dummy Bytes bits
0 Transmit zero dummy bytes after the address bytes
1 Transmit one dummy bytes after the address bytes
2 Transmit two dummy bytes after the address bytes
3 Transmit three dummy bytes after the address bytes
4 Transmit four dummy bytes after the address bytes
5 Transmit five dummy bytes after the address bytes
6 Transmit six dummy bytes after the address bytes
7 Transmit seven dummy bytes after the address bytes
ADDRBYTES
20:18
0 Zero address bytes
1 One address bytes
2 Two address bytes
3 Three address bytes
4 Four address bytes
5 Reserved
6 Reserved
7 Reserved
READOPCODE
17:10
These bits contain the 8-bit op code value for read operation.
TYPEDATA
9:8
The boot controller will receive the data in Single Lane, Dual Lane, or Quad Lane.
0 Single Lane mode data is enabled
1 Dual Lane mode data is enabled
2 Quad Lane mode data is enabled
3 Reserved
TYPEDUMMY
7:6
The boot controller will send the dummy in Single Lange, Dual Lane, or Quad Lane
0 Single Lange mode dummy is enabled
1 Dual Lane mode dummy is enabled
2 Quad Lane mode dummy is enabled
3 Reserved
TYPEMODE
5:4
The boot controller will send the mode in Single Lane, Dual Lane, or Quad Lane.
0 Single Lane mode is enabled
1 Dual Lane mode is enabled
2 Quad Lane mode is enabled
3 Reserved
TYPEADDR
3:2
The boot controller will send the address in Single Lane, Dual Lane, or Quad Lane.
0 Single Lane mode address is enabled
1 Dual Lane mode address is enabled
2 Quad Lane mode address is enabled
3 Reserved
TYPECMD
1:0
The boot controller will send the command in Single Lane, Dual Lane, or Quad Lane.
0 Single Lane mode command is enabled
1 Dual Lane mode command is enabled
2 Quad Lane mode command is enabled
3 Reserved
SQI1XCON2SQI XIP Control Register 2
Address
0xBF8E2004
Reset
0x000000A0
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
DEVSEL
11:10
Device Select bits
0 Device 0 is selected
1 Device 1 is selected
2 Reserved
3 Reserved
MODEBYTES
9:8
Mode Byte Cycle Enable bits
0 Zero cycles
1 One cycle
2 Two cycles
3 Three cycles
MODECODE
7:0
These bits contain the 8-bit code value for the mode bits.
SQI1CFGSQI Configuration Register
Address
0xBF8E2008
Reset
0x00008000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
CSEN
25:24
Chip Select Output Enable bits
0 Chip Select 0 and Chip Select 1 are not used
1 Chip Select 0 is used (Chip Select 1 is not used)
2 Chip Select 1 is used (Chip Select 0 is not used)
3 Chip Select 0 and Chip Select 1 are used
SQIEN
23
SQI Enable bit
0 SQI module is disabled
1 SQI module is enabled
DATAEN
21:20
Data Output Enable bits
0 SQID0 data output is enabled
1 SQID1 and SQID0 data outputs are enabled
2 SQID3-SQID0 outputs are enabled
3 Reserved
CONBUFRST
19
Control Buffer Reset bit
0 A reset pulse is not generated
1 A reset pulse is generated, clearing the control buffer
RXBUFRST
18
Receive Buffer Reset bit
0 A reset pulse is not generated
1 A reset pulse is generated clearing the receive buffer
TXBUFRST
17
Transmit Buffer Reset bit
0 A reset pulse is not generated
1 A reset pulse is generated clearing the transmit buffer
RESET
16
Software Reset Select bit
0 A reset pulse is not generated
1 A reset pulse is generated
BURSTEN
12
Burst Configuration bit
0 Burst is not enabled
1 Burst is enabled
HOLD
10
Hold bit. In Single Lane or Dual Lane mode, this bit is used to drive the SQID3 pin, which can be used for devices with a HOLD input pin. The meaning of the values for this bit will depend on the device to which SQID3 is connected.
WP
9
In Single Lane or Dual Lane mode, this bit is used to drive the SQID2 pin, which can be used with deviceswith a write-protect pin. The meaning of the values for this bit will depend on the device to which SQID2 isconnected.
LSBF
5
Data Format Select bit
0 MSB is sent or received first
1 LSB is send or received first
CPOL
4
Clock Polarity Select bit
0 Active-high SQICLK (SQICLK low is the Idle state)
1 Active-low SQICLK (SQICLK high is the Idle state)
CPHA
3
Clock Phase Select bit
0 SQICLK starts toggling at the middle of the first data bit
1 SQICLK starts toggling at the start of the first data bit
MODE
2:0
Mode Select bits
0 Reserved
1 CPU mode is selected (the module is controlled by the CPU in PIO mode. This mode is entered whenleaving Boot or XIP mode)
2 DMA mode is selected
3 XIP mode is selected (when this mode is entered, the module behaves as if executing in place (XIP),but uses the register data to control timing)
4 Reserved
5 Reserved
6 Reserved
7 Reserved
SQI1CONSQI Control Register
Address
0xBF8E200C
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
SCHECK
24
Flash Status Check bit
0 Do not check the status of the Flash
1 Check the status of the Flash
DDRMODE
23
Double Data Rate Mode bit
0 Set the SQI transfers to SDR mode
1 Set the SQI transfers to DDR mode
DASSERT
22
Chip Select Assert bit
0 Chip Select is not deasserted after transmission or reception of the specified number of bytes
1 Chip Select is deasserted after transmission or reception of the specified number of bytes
DEVSEL
21:20
SQI Device Select bits
0 Select Device 0
1 Select Device 1
2 Reserved
3 Reserved
LANEMODE
19:18
CMDINIT
17:16
TXRXCOUNT
15:0
SQI1CLKCONSQI Clock Control Register
Address
0xBF8E2010
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
CLKDIV
18:8
SQI Clock Tsqi Frequency Select bits
0 Base clock Tbc is divided by 2
1 Base clock Tbc is divided by 4
2 Base Clock Tbc is divided by 8
4 Base Clock Tbc is divided by 16
8 Base Clock Tbc is divided by 32
16 Base Clock Tbc is divided by 64
32 Base Clock Tbc is divided by 128
64 Base Clock Tbc is divided by 256
128 Base Clock Tbc is divided by 512
256 Base Clock Tbc is divided by 1024
512 Base Clock Tbc is divided by 2048
STABLE
1
Tsqi Clock Stable Select bit
0 Tsqi clock is not stable
1 Tsqi clock is stable
EN
0
Tsqi Clock Enable Select bit
0 Disable the SQI clock (Tsqi)
1 Enable the SQI clock (Tsqi)
SQI1CMDTHRSQI Command Threshold Register
Address
0xBF8E2014
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
TXCMDTHR
13:8
Transmit Command Threshold bits. Number of bytes in TX buffer at which to perform transmit operation. Should usually be '1' for normal Flash commands, and set to a higher value for page programming. For 16-bit mode, the value should be a multiple of 2.
RXCMDTHR
5:0
Receive Command Threshold bits. In receive initiation mode, the SQI module attempts to perform receive operations to fetch these number of bytes in the receive buffer. If software performs any reads, hardware would initiate a receive transfer to make the receive buffer count equal to the value in th
SQI1INTTHRSQI Interrupt Threshold Register
Address
0xBF8E2018
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
TXINTTHR
13:8
Transmit Interrupt Threshold bits. A transmit interrupt is set when the transmit buffer has more space than these number of bytes. For 16-bit mode, the value should be a multiple of 2.
RXINTTHR
5:0
Receive Interrupt Threshold bits. A receive interrupt is set when the buffer count is larger than or equal to this value. RXINTTHR is the number of bytes in the receive buffer. For 16-bit mode, the value should be a multiple of 2.
SQI1INTENSQI Interrupt Enable Register
Address
0xBF8E201C
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
DMAEIE
11
DMA Bus Error Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
PKTCOMPIE
10
DMA Buffer Descriptor Packet Complete Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
BDDONEIE
9
DMA Buffer Descriptor Done Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CONTHRIE
8
Control Buffer Threshold Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CONEMPTYIE
7
Control Buffer Empty Interrupt Enabled bit
0 Interrupt is disabled
1 Interrupt is enabled
CONFULLIE
6
Control Buffer Full Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
RXTHRIE
5
Receive Buffer Threshold Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
RXFULLIE
4
Receive Buffer Full Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
RXEMPTYIE
3
Receive Buffer Empty Interrupt Enabled bit
0 Interrupt is disabled
1 Interrupt is enabled
TXTHRIE
2
Transmit Buffer Threshold Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
TXFULLIE
1
Transmit Buffer Full Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
TXEMPTYIE
0
Transmit Buffer Empty Interrupt Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
SQI1INTSTAT
Address
0xBF8E2020
Reset
0x000000AD
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
DMAEIF
11
DMA Bus Error Interrupt Flag bit
0 DMA bus error has not occurred
1 DMA bus error has occurred
PKTCOMPIF
10
DMA Buffer Descriptor Processor Packet Complete Interrupt Status bit
0 DMA BD packet is in progress
1 DMA BD packet is complete
BDDONEIF
9
DMA Buffer Descriptor Done Interrupt Status bit
0 DMA BD process is in progress
1 DMA BD process is done
CONTHRIF
8
Control Buffer Threshold Interrupt Status bit
0 The control buffer has less than THRES words of space available
1 The control buffer has THRES or more words of space available
CONEMPTYIF
7
Control Buffer Empty Interrupt Status bit
0 Control buffer is not empty
1 Control buffer is empty
CONFULLIF
6
Control Buffer Full Interrupt Status bit
0 Control buffer is not full
1 Control buffer is full
RXTHRIF
5
Receive Buffer Threshold Interrupt Status bit
0 Receive buffer has less than RXINTTHR words of space available
1 Receive buffer has RXINTTHR or more words of space available
RXFULLIF
4
Receive Buffer Full Interrupt Status bit
0 Receive buffer is not full
1 Receive buffer is full
RXEMPTYIF
3
Receive Buffer Empty Interrupt Status bit
0 Receive buffer is not empty
1 Receive buffer is empty
TXTHRIF
2
Transmit Buffer Threshold Interrupt Status bit
0 Transmit buffer has less than TXINTTHR words of space available
1 Transmit buffer has more than TXINTTHR words of space available
TXFULLIF
1
Transmit Buffer Full Interrupt Status bit
0 The transmit buffer is not full
1 The transmit buffer is full
TXEMPTYIF
0
Transmit Buffer Empty Interrupt Status bit
0 The transmit buffer has content
1 The transmit buffer is empty
SQI1TXDATASQI Transmit Data Buffer Register
Address
0xBF8E2024
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXDATA
31:0
Transmit Command Data bits. Data is loaded into this register before being transmitted.
SQI1RXDATASQI Receive Data Buffer Register
Address
0xBF8E2028
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
RXDATA
31:0
Receive Data Buffer bits. At the end of a data transfer, the data in the shift register is loaded into the RXDATA register. This register works like a buffer.
SQI1STAT1SQI Status Register 1
Address
0xBF8E202C
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
TXBUFFREE
21:16
Transmit Buffer Available Word Space bits
RXBUFCNT
5:0
Number of words of read data in the buffer.
SQI1STAT2SQI Status Register 2
Address
0xBF8E2030
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
Field
Bits
What it does
CMDSTAT
17:16
Current Command Status bits
0 Idle
1 Transmit
2 Receive
3 Reserved
CONAVAIL
10:7
Control IFO Space Available bits
0 No bytes are available
1 1 byte is available
30 31 bytes are available
31 32 bytes are available
SQID3
6
SQID3 Status bit
0 Data is not present on SQID3
1 Data is present on SQID3
SQID2
5
SQID2 Status bit
0 Data is not present on SQID2
1 Data is present on SQID2
SQID1
4
SQID1 Status bit
0 Data is not present on SQID1
1 Data is present on SQID1
SQID0
3
SQID0 Status bit
0 Data is not present on SQID0
1 Data is present on SQID0
RXUN
1
Receive Buffer Underflow Status bit
0 Receive Buffer Underflow has not occurred
1 Receive Buffer Underflow has occurred
TXOV
0
Transmit Buffer Overflow Status bit
0 Transmit Buffer overflow has not occurred
1 Transmit Buffer overflow has occurred
SQI1BDCONSQI Buffer Descriptor Control Register
Address
0xBF8E2034
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
START
2
Buffer Descriptor Processor Start bit
0 Disable the buffer descriptor processor
1 Start the buffer descriptor processor
POLLEN
1
Buffer Descriptor Poll Enable bit
0 BDP poll is not enabled
1 BDP poll enabled
DMAEN
0
DMA Enable bit
0 DMA is disabled
1 DMA is enabled
SQI1BDCURADDSQI Buffer Descriptor Current Address Register
Address
0xBF8E2038
Reset
0x01000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
BDCURRADDR
31:0
The address in physical memory of the current descriptor being processed by the Buffer Descriptor Processor.
SQI1BDBASEADDSQI Buffer Descriptor Base Address Register
Address
0xBF8E2040
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
BDADDR
31:0
The address in physical memory of the first buffer descriptor. This register should be updated only when the DMA is idle.
SQI1BDSTATSQI Buffer Descriptor Status Register
Address
0xBF8E2044
Reset
0x00000000
Access
read only
Size
32-bit
4 fields
Field
Bits
What it does
BDSTATE
21:18
DMA Buffer Descriptor Processor State Status bits
0 Idle
1 Descriptor fetch request is pending
2 Buffer descriptor is loading
3 Data phase
4 Descriptor is done
5 Fetched buffer descriptor is disabled
6 Reserved
7 Reserved
8 Reserved
DMASTART
17
DMA Buffer Descriptor Processor Start Status bit
0 DMA has not started
1 DMA has started
DMAACTV
16
DMA Buffer Descriptor Processor Active Status bit
0 Buffer Descriptor Processor is idle
1 Buffer Descriptor Processor is active
BDCON
15:0
DMA Buffer Descriptor Control Word bits. These bits contain the current buffer descriptor control word.
SQI1BDPOLLCONSQI Buffer Descriptor Poll Control Register
Address
0xBF8E2048
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
POLLCON
15:0
Buffer Descriptor Processor Poll Status bits. These bits indicate the number of cycles the BDP would wait before refetching the descriptor control word if the previous descriptor fetched was disabled.
SQI1BDTXDSTATSQI Buffer Descriptor DMA Transmit Status Register
Address
0xBF8E204C
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
TXSTATE
28:25
Current DMA Transmit State Status bits
TXBUFCNT
20:16
DMA Buffer Byte Count Status bits
TXCURBUFLEN
8:0
Current DMA Transmit Buffer Length Status bits.
SQI1BDRXDSTATSQI Buffer Descriptor DMA Receive Status Register
Address
0xBF8E2050
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
RXSTATE
28:25
Current DMA Receive State Status bits.
RXBUFCNT
20:16
DMA Buffer Byte Count Status bits.
RXCURBUFLEN
8:0
Current DMA Receive Buffer Length Status bits.
SQI1THRSQI Threshold Control Register
Address
0xBF8E2054
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
THRES
3:0
SQI Control Threshold Value bits. The SQI control threshold interrupt is asserted when the amount of space indicated by THRES<6:0> is available in the SQI control buffer.
SQI1INTSIGENSQI Interrupt Signal Enable Register
Address
0xBF8E2058
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
DMAEISE
11
DMA Bus Error Interrupt Signal Enable bit
0 Interrupt signal is disabled
1 Interrupt signal is enabled
PKTCOMPISE
10
DMA Buffer Descriptor Packet Complete Interrupt Signal Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
BDDONEISE
9
DMA Buffer Descriptor Done Interrupt Signal Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CONTHRISE
8
Control Buffer Threshold Interrupt Signal Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CONEMPTYISE
7
Control Buffer Empty Interrupt Signal Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
CONFULLISE
6
Control Buffer Full Interrupt Signal Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
RXTHRISE
5
Receive Buffer Threshold Interrupt Signal Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
RXFULLISE
4
Receive Buffer Full Interrupt Signal Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
RXEMPTYISE
3
Receive Buffer Empty Interrupt Signal Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
TXTHRISE
2
Transmit Buffer Threshold Interrupt Signal Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
TXFULLISE
1
Transmit Buffer Full Interrupt Signal Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
TXEMPTYISE
0
Transmit Buffer Empty Interrupt Signal Enable bit
0 Interrupt is disabled
1 Interrupt is enabled
SQI1TAPCONSQI Tap Control Register
Address
0xBF8E205C
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
DDRCLKINDLY
29:24
SDRDATINDLY
23:20
DDRDATINDLY
19:16
SDRCLKINDLY
13:8
SQI Clock Input Delay bits
0 1 tap added on clock input
1 2 taps added on clock input
62 63 taps added on clock input
63 64 taps added on clock input
DATAOUTDLY
7:4
SQI Data Output Delay bits
0 1 tap added on clock output
1 2 taps added on clock output
14 15 taps added on clock output
15 16 taps added on clock output
CLKOUTDLY
3:0
SQI Clock Output Delay bits
0 1 tap added on clock output
1 2 taps added on clock output
14 15 taps added on clock output
15 16 taps added on clock output
SQI1MEMSTATSQI Memory Status Register
Address
0xBF8E2060
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
STATPOS
20
Statis Bit Position in Flash bit
0 BUSY bit position is bit 0 in status register
1 BUSY bit position is bit 7 in status register
STATTYPE
19:18
Status Command/Read Lane Mode bits
0 Status command and read are executed in Single Lane mode
1 Status command and read are executed in Dual Lane mode
2 Status command and read are executed in Quad Lane mode
3 Reserved
STATBYTES
17:16
Number of Status Bytes bits
0 Reserved
1 Status command/read is 1 byte long
2 Status command/read is 2 bytes long
3 Reserved
STATCMD
15:0
Status Command bits. The status check command is written into these bits.
SQI1XCON3SQI XIP Control Register 3
Address
0xBF8E2064
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
INIT1SCHECK
28
Flash Initialization 1 Command Status Check bit
0 Do not check the status
1 Check the status after executing the INIT1 command
INIT1COUNT
27:26
Flash Initialization 1 Command Count bits
0 No commands are sent
1 INIT1CMD1 is sent, but INIT1CMD2 and INIT1CMD3 are still pending.
2 INIT1CMD1 and INIT1CMD2 are sent, but INIT1CMD3 is still pending.
3 INIT1CMD3, INIT1CMD2, and INIT1CMD3 are sent.
INIT1TYPE
25:24
Flash Initialization 1 Command Type bits
0 INIT1 commadns are sent in Single Lane mode
1 INIT1 commands are sent in Dual Lane mode
2 INIT1 commands are sent in Quad Lane mode
3 Reserved
INIT1CMD3
23:16
Flash Initialization Command 3 bits. Third command of the Flash initialization.
INIT1CMD2
15:8
Flash Initialization Command 2 bits. Second command of the Flash initialization.
INIT1CMD1
7:0
Flash Initialization Command 1 bits. First command of the Flash initialization.
SQI1XCON4SQI XIP Control Register 4
Address
0xBF8E2068
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
INIT2SCHECK
28
Flash Initialization 2 Command Status Check bit
0 Do not check the status
1 Check the status after executing the INIT2 command
INIT2COUNT
27:26
Flash Initialization 2 Command Count bits
0 No commands are sent
1 INIT2CMD1 is sent, but INIT2CMD2 and INIT2CMD3 are still pending
2 INIT2CMD1 and INIT2CMD2 are sent, but INIT2CMD3 is still pending
3 INIT2CMD1, INIT2CMD2, and INIT2CMD3 are sent
INIT2TYPE
25:24
Flash Initialization 2 Command Type bits
0 INIT2 commands are sent in Single Lane mode
1 INIT2 commands are sent in Dual Lane mode
2 INIT2 commands are sent in Quad Lane mode
3 Reserved
INIT2CMD3
23:16
Flash Initialization Command 3 bits. Third command of the Flash initialization.
INIT2CMD2
15:8
Flash Initialization Command 2 bits. Second command of the Flash initialization.
INIT2CMD1
7:0
Flash Initialization Command 1 bits. First command of the Flash initialization.
BETA