PIC32MZ1064DAR176 PORTE registers

The 14 registers of PORTE (I/O port E), from 0xBF860400, with their reset value and every field. The PIC32MZ1064DAR176 has 2308 registers in 102 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

PORTE I/O port E

ANSELE

Address: 0xBF860400
Reset: 0x000003D2
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
ANSE9	9
ANSE8	8
ANSE7	7
ANSE6	6
ANSE4	4
ANSE1	1

TRISE

Address: 0xBF860410
Reset: 0x000003FF
Access: read/write
Size: 32-bit

10 fields

Field	Bits	What it does
TRISE9	9
TRISE8	8
TRISE7	7
TRISE6	6
TRISE5	5
TRISE4	4
TRISE3	3
TRISE2	2
TRISE1	1
TRISE0	0

PORTE

Address: 0xBF860420
Reset: 0x00000000
Access: read/write
Size: 32-bit

10 fields

Field	Bits	What it does
RE9	9
RE8	8
RE7	7
RE6	6
RE5	5
RE4	4
RE3	3
RE2	2
RE1	1
RE0	0

LATE

Address: 0xBF860430
Reset: 0x00000000
Access: read/write
Size: 32-bit

10 fields

Field	Bits	What it does
LATE9	9
LATE8	8
LATE7	7
LATE6	6
LATE5	5
LATE4	4
LATE3	3
LATE2	2
LATE1	1
LATE0	0

ODCE

Address: 0xBF860440
Reset: 0x00000000
Access: read/write
Size: 32-bit

10 fields

Field	Bits	What it does
ODCE9	9
ODCE8	8
ODCE7	7
ODCE6	6
ODCE5	5
ODCE4	4
ODCE3	3
ODCE2	2
ODCE1	1
ODCE0	0

CNPUE

Address: 0xBF860450
Reset: 0x00000000
Access: read/write
Size: 32-bit

10 fields

Field	Bits	What it does
CNPUE9	9
CNPUE8	8
CNPUE7	7
CNPUE6	6
CNPUE5	5
CNPUE4	4
CNPUE3	3
CNPUE2	2
CNPUE1	1
CNPUE0	0

CNPDE

Address: 0xBF860460
Reset: 0x00000000
Access: read/write
Size: 32-bit

10 fields

Field	Bits	What it does
CNPDE9	9
CNPDE8	8
CNPDE7	7
CNPDE6	6
CNPDE5	5
CNPDE4	4
CNPDE3	3
CNPDE2	2
CNPDE1	1
CNPDE0	0

CNCONEChange Notice control for PORTx Register

Address: 0xBF860470
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
ON	15	Change Notice Control ON bit `0` CN is disabled `1` CN is enabled
EDGEDETECT	11	Change Notification Style bit `0` Mismatch Style. Detect change from last PORTx read (CNSTATx used for CN Event). `1` Edge Style. Detect edge transitions (CNFx used for CN Event).

CNENE

Address: 0xBF860480
Reset: 0x00000000
Access: read/write
Size: 32-bit

10 fields

Field	Bits	What it does
CNIEE9	9
CNIEE8	8
CNIEE7	7
CNIEE6	6
CNIEE5	5
CNIEE4	4
CNIEE3	3
CNIEE2	2
CNIEE1	1
CNIEE0	0

CNSTATE

Address: 0xBF860490
Reset: 0x00000000
Access: read/write
Size: 32-bit

10 fields

Field	Bits	What it does
CNSTATE9	9
CNSTATE8	8
CNSTATE7	7
CNSTATE6	6
CNSTATE5	5
CNSTATE4	4
CNSTATE3	3
CNSTATE2	2
CNSTATE1	1
CNSTATE0	0

CNNEE

Address: 0xBF8604A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

10 fields

Field	Bits	What it does
CNNEE9	9
CNNEE8	8
CNNEE7	7
CNNEE6	6
CNNEE5	5
CNNEE4	4
CNNEE3	3
CNNEE2	2
CNNEE1	1
CNNEE0	0

CNFE

Address: 0xBF8604B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

10 fields

Field	Bits	What it does
CNFE9	9
CNFE8	8
CNFE7	7
CNFE6	6
CNFE5	5
CNFE4	4
CNFE3	3
CNFE2	2
CNFE1	1
CNFE0	0

SRCON0E

Address: 0xBF8604C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

10 fields

Field	Bits	What it does
SR0E9	9
SR0E8	8
SR0E7	7
SR0E6	6
SR0E5	5
SR0E4	4
SR0E3	3
SR0E2	2
SR0E1	1
SR0E0	0

SRCON1E

Address: 0xBF8604D0
Reset: 0x00000000
Access: read/write
Size: 32-bit

10 fields

Field	Bits	What it does
SR1E9	9
SR1E8	8
SR1E7	7
SR1E6	6
SR1E5	5
SR1E4	4
SR1E3	3
SR1E2	2
SR1E1	1
SR1E0	0