PIC32MZ2025DAB288 CFG registers

The 8 registers of CFG (Configuration and pin control), from 0xBF800000, with their reset value and every field. The PIC32MZ2025DAB288 has 2318 registers in 103 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

CFG Configuration and pin control

CFGCONConfiguration Control Register

Address
0xBF800000
Reset
0x00000031
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
ICACLK17Input Capture Alternate Clock Selection bit(1)
  • 0 All Input Capture modules use Timer2/3 as their timebase clock
  • 1 Input Capture modules use an alternative Timer pair as their timebase clock
OCACLK16Output Compare Alternate Clock Selection bit(1)
  • 0 All Output Compare modules use Timer2/3 as their timebase clock
  • 1 Output Compare modules use an alternative Timer pair as their timebase clock
IOLOCK13Peripheral Pin Select Lock bit(1)
  • 0 Peripheral Pin Select is not locked. Writes to PPS registers is allowed.
  • 1 Peripheral Pin Select is locked. Writes to PPS registers is not allowed.
PMDLOCK12Peripheral Module Disable bit(1)
  • 0 Peripheral module is not locked. Writes to PMD registers is allowed.
  • 1 Peripheral module is locked. Writes to PMD registers is not allowed.
PGLOCK11Permission Group Lock bit(1)
  • 0 Permission Group registers are not locked. Writes to PG registers are allowed.
  • 1 Permission Group registers are locked. Writes to PG registers are not allowed.
USBSSEN8USB Suspend Sleep Enable bit(1)
  • 0 USB PHY clock continues to run when Sleep is active
  • 1 USB PHY clock is shut down when Sleep mode is active
IOANCPEN7I/O Analog Charge Pump Enable bit
  • 0 Charge pumps are disabled
  • 1 Charge pumps are enabled
ECCCON5:4Flash ECC Configuration bits
  • 0 Flash ECC is enabled (ECCCON bits are locked; disables word Flash writes)
  • 1 Dynamic Flash ECC is enabled (ECCCON bits are locked)
  • 2 ECC and dynamic ECC are disabled (ECCCON bits are locked)
  • 3 ECC and dynamic ECC are disabled (ECCCON bits are writable)
JTAGEN3JTAG Port Enable bit
  • 0 Disable the JTAG port
  • 1 Enable the JTAG port
TROEN2Trace Output Enable bit
  • 0 Disable trace outputs and stop trace clock
  • 1 Enable trace outputs and start trace clock (trace probe must be present)
TDOEN0TDO Enable for 2-Wire JTAG
  • 0 2-wire JTAG protocol does not use TDO
  • 1 2-wire JTAG protocol uses TDO

DEVIDDevice and Revision ID Register

Address
0xBF800020
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
DEVID27:0
VER31:28

SYSKEY

Address
0xBF800030
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SYSKEY31:0

CFGEBIAExternal Bus Interface Address Pin Configuration Register

Address
0xBF8000C0
Reset
0x00000000
Access
read/write
Size
32-bit
24 fields
FieldBitsWhat it does
EBIA23EN23EBI Address Pin Enable bit 23
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA22EN22EBI Address Pin Enable bit 22
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA21EN21EBI Address Pin Enable bit 21
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA20EN20EBI Address Pin Enable bit 20
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA19EN19EBI Address Pin Enable bit 19
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA18EN18EBI Address Pin Enable bit 18
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA17EN17EBI Address Pin Enable bit 17
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA16EN16EBI Address Pin Enable bit 16
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA15EN15EBI Address Pin Enable bit 15
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA14EN14EBI Address Pin Enable bit 14
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA13EN13EBI Address Pin Enable bit 13
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA12EN12EBI Address Pin Enable bit 12
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA11EN11EBI Address Pin Enable bit 11
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA10EN10EBI Address Pin Enable bit 10
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA9EN9EBI Address Pin Enable bit 9
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA8EN8EBI Address Pin Enable bit 8
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA7EN7EBI Address Pin Enable bit 7
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA6EN6EBI Address Pin Enable bit 6
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA5EN5EBI Address Pin Enable bit 5
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA4EN4EBI Address Pin Enable bit 4
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA3EN3EBI Address Pin Enable bit 3
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA2EN2EBI Address Pin Enable bit 2
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA1EN1EBI Address Pin Enable bit 1
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI
EBIA0EN0EBI Address Pin Enable bit 0
  • 0 EBIAx pin has is available for general use
  • 1 EBIAx pin is enabled for use by EBI

CFGEBICExternal Bus Interface Control Pin Configuration Register

Address
0xBF8000D0
Reset
0x00000000
Access
read/write
Size
32-bit
18 fields
FieldBitsWhat it does
EBIRDYINV230EBIRDY2 Inversion Control bit
  • 0 Do not invert EBIRDY2 pin before use
  • 1 Invert EBIRDY2 pin before use
EBIRDYINV129EBIRDY1 Inversion Control bit
  • 0 Do not invert EBIRDY1 pin before use
  • 1 Invert EBIRDY1 pin before use
EBIRDYEN327EBIRDY3 Pin Enable bit
  • 0 EBIRDY3 pin is available for general use
  • 1 EBIRDY3 pin is enabled for use by the EBI module
EBIRDYEN226EBIRDY2 Pin Enable bit
  • 0 EBIRDY2 pin is available for general use
  • 1 EBIRDY2 pin is enabled for use by the EBI module
EBIRDYEN125EBIRDY1 Pin Enable bit
  • 0 EBIRDY1 pin is available for general use
  • 1 EBIRDY1 pin is enabled for use by the EBI module
EBIRDYLVL17EBIRDYx Pin Sensitivity Control bit
  • 0 Use edge detect for EBIRDYx pins
  • 1 Use level detect for EBIRDYx pins
EBIRPEN16EBIRP Pin Sensitivity Control bit
  • 0 EBIRP pin is available for general use
  • 1 EBIRP pin is enabled for use by the EBI module
EBIWEEN13EBIWE Pin Enable bit
  • 0 EBIWE pin is available for general use
  • 1 EBIWE pin is enabled for use by the EBI module
EBIOEEN12EBIOE Pin Enable bit
  • 0 EBIOE pin is available for general use
  • 1 EBIOE pin is enabled for use by the EBI module
EBIBSEN19EBIBS1 Pin Enable bit
  • 0 EBIBS1 pin is available for general use
  • 1 EBIBS1 pin is enabled for use by the EBI module
EBIBSEN08EBIBS0 Pin Enable bit
  • 0 EBIBS0 pin is available for general use
  • 1 EBIBS0 pin is enabled for use by the EBI module
EBICSEN37EBICS3 Pin Enable bit
  • 0 EBICS3 pin is available for general use
  • 1 EBICS3 pin is enabled for use by the EBI module
EBICSEN26EBICS2 Pin Enable bit
  • 0 EBICS2 pin is available for general use
  • 1 EBICS2 pin is enabled for use by the EBI module
EBICSEN15EBICS1 Pin Enable bit
  • 0 EBICS1 pin is available for general use
  • 1 EBICS1 pin is enabled for use by the EBI module
EBICSEN04EBICS0 Pin Enable bit
  • 0 EBICS0 pin is available for general use
  • 1 EBICS0 pin is enabled for use by the EBI module
EBIDEN11EBI Data Upper Byte Pin Enable bit
  • 0 EBID pins have reverted to general use
  • 1 EBID pins are enabled for use by the EBI module
EBIDEN00EBI Data Upper Byte Pin Enable bit
  • 0 EBID pins have reverted to general use
  • 1 EBID pins are enabled for use by the EBI module
EBIRDYINV331EBIRDY3 Inversion Control bit
  • 0 Do not invert EBIRDY3 pin before use
  • 1 Invert EBIRDY3 pin before use

CFGPGPermission Group Configuration Register

Address
0xBF8000E0
Reset
0x00000000
Access
read/write
Size
32-bit
13 fields
FieldBitsWhat it does
GPUPG29:282D Graphics Processing Unit Permission Group bits
  • 0 Initiator is assigned to Permission Group 0
  • 1 Initiator is assigned to Permission Group 1
  • 2 Initiator is assigned to Permission Group 2
  • 3 Initiator is assigned to Permission Group 3
GLCDPG27:26Graphics LCD Controller Permission Group bits
  • 0 Initiator is assigned to Permission Group 0
  • 1 Initiator is assigned to Permission Group 1
  • 2 Initiator is assigned to Permission Group 2
  • 3 Initiator is assigned to Permission Group 3
CRYPTPG25:24Crypto Engine Permission Group bits
  • 0 Initiator is assigned to Permission Group 0
  • 1 Initiator is assigned to Permission Group 1
  • 2 Initiator is assigned to Permission Group 2
  • 3 Initiator is assigned to Permission Group 3
FCPG23:22Flash Control Permission Group bits
  • 0 Initiator is assigned to Permission Group 0
  • 1 Initiator is assigned to Permission Group 1
  • 2 Initiator is assigned to Permission Group 2
  • 3 Initiator is assigned to Permission Group 3
SQI1PG21:20SQI Module Permission Group bits
  • 0 Initiator is assigned to Permission Group 0
  • 1 Initiator is assigned to Permission Group 1
  • 2 Initiator is assigned to Permission Group 2
  • 3 Initiator is assigned to Permission Group 3
SDHCPG19:18Secure Digital Host Controller Permission Group bits
  • 0 Initiator is assigned to Permission Group 0
  • 1 Initiator is assigned to Permission Group 1
  • 2 Initiator is assigned to Permission Group 2
  • 3 Initiator is assigned to Permission Group 3
ETHPG17:16Ethernet Module Permission Group bits
  • 0 Initiator is assigned to Permission Group 0
  • 1 Initiator is assigned to Permission Group 1
  • 2 Initiator is assigned to Permission Group 2
  • 3 Initiator is assigned to Permission Group 3
CAN2PG15:14CAN2 Module Permission Group bits
  • 0 Initiator is assigned to Permission Group 0
  • 1 Initiator is assigned to Permission Group 1
  • 2 Initiator is assigned to Permission Group 2
  • 3 Initiator is assigned to Permission Group 3
CAN1PG13:12CAN1 Module Permission Group bits
  • 0 Initiator is assigned to Permission Group 0
  • 1 Initiator is assigned to Permission Group 1
  • 2 Initiator is assigned to Permission Group 2
  • 3 Initiator is assigned to Permission Group 3
USBPG9:8USB Module Permission Group bits
  • 0 Initiator is assigned to Permission Group 0
  • 1 Initiator is assigned to Permission Group 1
  • 2 Initiator is assigned to Permission Group 2
  • 3 Initiator is assigned to Permission Group 3
DMAPG5:4DMA Module Permission Group bits
  • 0 Initiator is assigned to Permission Group 0
  • 1 Initiator is assigned to Permission Group 1
  • 2 Initiator is assigned to Permission Group 2
  • 3 Initiator is assigned to Permission Group 3
CPUPG1:0CPU Permission Group bits
  • 0 Initiator is assigned to Permission Group 0
  • 1 Initiator is assigned to Permission Group 1
  • 2 Initiator is assigned to Permission Group 2
  • 3 Initiator is assigned to Permission Group 3
ICD1PG31:30

CFGCON2Configuration Control Register 2

Address
0xBF8000F0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
GLCDMODE30Graphics Display Mode bit
  • 0 GLCD pins are set to RGB888 mode
  • 1 GLCD pins are set to RGB565 mode. Other GDx pins are available for general purpose use.
SDCDEN29SD Card Detect Pin Enable bit
  • 0 SDCD pin is available for general purpose use
  • 1 SDCD pin is enabled for use by SDHC
SDWPEN28SD card Write Protect Enable bit
  • 0 SDWP pin is available for general purpose use
  • 1 SDWP pin is enabled for use by SDHC
SDWRFTHR25:16SDHC Write FIFO Threshold bits
SDRDFTHR13:4SDHC Read FIFO Threshold bits
SDWPPOL2SDWPPOL
  • 0 SDWP pin is Active-Low
  • 1 SDWP pin is Active-High
GPURESET0GPU Reset Bit
  • 0 Release RESET to the GPU module
  • 1 Hold GPU in RESET
GLCDPINEN31Graphics Display Pin Enable bit
  • 0 GLCD pins are available for general purpose use
  • 1 GLCD pins are used by the GLCD module

CFGMPLLMemory PLL Configuration Register

Address
0xBF800100
Reset
0xFD03FFFF
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
MPLLDIS30MPLL Disable bit
  • 0 MPLL is enabled
  • 1 MPLL is disabled
MPLLODIV229:27MPLL Output Divider 2 bits
  • 0 Reserved
  • 1 MPLL second stage output is divided by 1
  • 2 MPLL second stage output is divided by 2
  • 3 MPLL second stage output is divided by 3
  • 4 MPLL second stage output is divided by 4
  • 5 MPLL second stage output is divided by 5
  • 6 MPLL second stage output is divided by 6
  • 7 MPLL second stage output is divided by 7
MPLLODIV126:24MPLL Output Divider 1 bits
  • 0 Reserved
  • 1 MPLL second stage output is divided by 1
  • 2 MPLL second stage output is divided by 2
  • 3 MPLL second stage output is divided by 3
  • 4 MPLL second stage output is divided by 4
  • 5 MPLL second stage output is divided by 5
  • 6 MPLL second stage output is divided by 6
  • 7 MPLL second stage output is divided by 7
MPLLVREGRDY23MPLL Voltage Regulator Ready bit
  • 0 MPLL voltage regulator is not ready or is disabled
  • 1 MPLL voltage regulator is ready for use
MPLLVREGDIS22MPLL Voltage regulator Disable bit
  • 0 MPLL voltage regulator is enabled
  • 1 MPLL voltage regulator is disabled
MPLLMULT15:8MPLL Multiplier bits
  • 0 Reserved
  • 1 Reserved
  • 2 Reserved
  • 3 Reserved
  • 4 Reserved
  • 5 Reserved
  • 6 Reserved
  • 7 Reserved
  • 8 Reserved
  • 9 Reserved
  • 10 Reserved
  • 11 Reserved
  • 12 Reserved
  • 13 Reserved
  • 14 Reserved
  • 15 Reserved
  • 16 Multiply by 16
  • 17 Multiply by 17
  • 18 Multiply by 18
  • 19 Multiply by 19
  • 20 Multiply by 20
  • 21 Multiply by 21
  • 22 Multiply by 22
  • 23 Multiply by 23
  • 24 Multiply by 24
  • 25 Multiply by 25
  • 26 Multiply by 26
  • 27 Multiply by 27
  • 28 Multiply by 28
  • 29 Multiply by 29
  • 30 Multiply by 30
  • 31 Multiply by 31
  • 32 Multiply by 32
  • 33 Multiply by 33
  • 34 Multiply by 34
  • 35 Multiply by 35
  • 36 Multiply by 36
  • 37 Multiply by 37
  • 38 Multiply by 38
  • 39 Multiply by 39
  • 40 Multiply by 40
  • 41 Multiply by 41
  • 42 Multiply by 42
  • 43 Multiply by 43
  • 44 Multiply by 44
  • 45 Multiply by 45
  • 46 Multiply by 46
  • 47 Multiply by 47
  • 48 Multiply by 48
  • 49 Multiply by 49
  • 50 Multiply by 50
  • 51 Multiply by 51
  • 52 Multiply by 52
  • 53 Multiply by 53
  • 54 Multiply by 54
  • 55 Multiply by 55
  • 56 Multiply by 56
  • 57 Multiply by 57
  • 58 Multiply by 58
  • 59 Multiply by 59
  • 60 Multiply by 60
  • 61 Multiply by 61
  • 62 Multiply by 62
  • 63 Multiply by 63
  • 64 Multiply by 64
  • 65 Multiply by 65
  • 66 Multiply by 66
  • 67 Multiply by 67
  • 68 Multiply by 68
  • 69 Multiply by 69
  • 70 Multiply by 70
  • 71 Multiply by 71
  • 72 Multiply by 72
  • 73 Multiply by 73
  • 74 Multiply by 74
  • 75 Multiply by 75
  • 76 Multiply by 76
  • 77 Multiply by 77
  • 78 Multiply by 78
  • 79 Multiply by 79
  • 80 Multiply by 80
  • 81 Multiply by 81
  • 82 Multiply by 82
  • 83 Multiply by 83
  • 84 Multiply by 84
  • 85 Multiply by 85
  • 86 Multiply by 86
  • 87 Multiply by 87
  • 88 Multiply by 88
  • 89 Multiply by 89
  • 90 Multiply by 90
  • 91 Multiply by 91
  • 92 Multiply by 92
  • 93 Multiply by 93
  • 94 Multiply by 94
  • 95 Multiply by 95
  • 96 Multiply by 96
  • 97 Multiply by 97
  • 98 Multiply by 98
  • 99 Multiply by 99
  • 100 Multiply by 100
  • 101 Multiply by 101
  • 102 Multiply by 102
  • 103 Multiply by 103
  • 104 Multiply by 104
  • 105 Multiply by 105
  • 106 Multiply by 106
  • 107 Multiply by 107
  • 108 Multiply by 108
  • 109 Multiply by 109
  • 110 Multiply by 110
  • 111 Multiply by 111
  • 112 Multiply by 112
  • 113 Multiply by 113
  • 114 Multiply by 114
  • 115 Multiply by 115
  • 116 Multiply by 116
  • 117 Multiply by 117
  • 118 Multiply by 118
  • 119 Multiply by 119
  • 120 Multiply by 120
  • 121 Multiply by 121
  • 122 Multiply by 122
  • 123 Multiply by 123
  • 124 Multiply by 124
  • 125 Multiply by 125
  • 126 Multiply by 126
  • 127 Multiply by 127
  • 128 Multiply by 128
  • 129 Multiply by 129
  • 130 Multiply by 130
  • 131 Multiply by 131
  • 132 Multiply by 132
  • 133 Multiply by 133
  • 134 Multiply by 134
  • 135 Multiply by 135
  • 136 Multiply by 136
  • 137 Multiply by 137
  • 138 Multiply by 138
  • 139 Multiply by 139
  • 140 Multiply by 140
  • 141 Multiply by 141
  • 142 Multiply by 142
  • 143 Multiply by 143
  • 144 Multiply by 144
  • 145 Multiply by 145
  • 146 Multiply by 146
  • 147 Multiply by 147
  • 148 Multiply by 148
  • 149 Multiply by 149
  • 150 Multiply by 150
  • 151 Multiply by 151
  • 152 Multiply by 152
  • 153 Multiply by 153
  • 154 Multiply by 154
  • 155 Multiply by 155
  • 156 Multiply by 156
  • 157 Multiply by 157
  • 158 Multiply by 158
  • 159 Multiply by 159
  • 160 Multiply by 160
  • 161 Reserved
  • 162 Reserved
  • 163 Reserved
  • 164 Reserved
  • 165 Reserved
  • 166 Reserved
  • 167 Reserved
  • 168 Reserved
  • 169 Reserved
  • 170 Reserved
  • 171 Reserved
  • 172 Reserved
  • 173 Reserved
  • 174 Reserved
  • 175 Reserved
  • 176 Reserved
  • 177 Reserved
  • 178 Reserved
  • 179 Reserved
  • 180 Reserved
  • 181 Reserved
  • 182 Reserved
  • 183 Reserved
  • 184 Reserved
  • 185 Reserved
  • 186 Reserved
  • 187 Reserved
  • 188 Reserved
  • 189 Reserved
  • 190 Reserved
  • 191 Reserved
  • 192 Reserved
  • 193 Reserved
  • 194 Reserved
  • 195 Reserved
  • 196 Reserved
  • 197 Reserved
  • 198 Reserved
  • 199 Reserved
  • 200 Reserved
  • 201 Reserved
  • 202 Reserved
  • 203 Reserved
  • 204 Reserved
  • 205 Reserved
  • 206 Reserved
  • 207 Reserved
  • 208 Reserved
  • 209 Reserved
  • 210 Reserved
  • 211 Reserved
  • 212 Reserved
  • 213 Reserved
  • 214 Reserved
  • 215 Reserved
  • 216 Reserved
  • 217 Reserved
  • 218 Reserved
  • 219 Reserved
  • 220 Reserved
  • 221 Reserved
  • 222 Reserved
  • 223 Reserved
  • 224 Reserved
  • 225 Reserved
  • 226 Reserved
  • 227 Reserved
  • 228 Reserved
  • 229 Reserved
  • 230 Reserved
  • 231 Reserved
  • 232 Reserved
  • 233 Reserved
  • 234 Reserved
  • 235 Reserved
  • 236 Reserved
  • 237 Reserved
  • 238 Reserved
  • 239 Reserved
  • 240 Reserved
  • 241 Reserved
  • 242 Reserved
  • 243 Reserved
  • 244 Reserved
  • 245 Reserved
  • 246 Reserved
  • 247 Reserved
  • 248 Reserved
  • 249 Reserved
  • 250 Reserved
  • 251 Reserved
  • 252 Reserved
  • 253 Reserved
  • 254 Reserved
  • 255 Reserved
INTVREFCON7:6Internal DDRV
  • 0 Use the external DDRV
  • 1 Disable the internal DDRV and drive the DDRVREF pin to VDDR1V8
  • 2 Disable the internal DDRV and drive the DDRVREF pin to VSS1V8
  • 3 Enable the internal DDRV
MPLLIDIV5:0MPLL Input Divider bits
  • 0 Reserved
  • 1 MPLL input clock is divider by 1
  • 2 MPLL input clock is divider by 2
  • 3 MPLL input clock is divider by 3
  • 4 MPLL input clock is divider by 4
  • 5 MPLL input clock is divider by 5
  • 6 MPLL input clock is divider by 6
  • 7 MPLL input clock is divider by 7
  • 8 MPLL input clock is divider by 8
  • 9 MPLL input clock is divider by 9
  • 10 MPLL input clock is divider by 10
  • 11 MPLL input clock is divider by 11
  • 12 MPLL input clock is divider by 12
  • 13 MPLL input clock is divider by 13
  • 14 MPLL input clock is divider by 14
  • 15 MPLL input clock is divider by 15
  • 16 MPLL input clock is divider by 16
  • 17 MPLL input clock is divider by 17
  • 18 MPLL input clock is divider by 18
  • 19 MPLL input clock is divider by 19
  • 20 MPLL input clock is divider by 20
  • 21 MPLL input clock is divider by 21
  • 22 MPLL input clock is divider by 22
  • 23 MPLL input clock is divider by 23
  • 24 MPLL input clock is divider by 24
  • 25 MPLL input clock is divider by 25
  • 26 MPLL input clock is divider by 26
  • 27 MPLL input clock is divider by 27
  • 28 MPLL input clock is divider by 28
  • 29 MPLL input clock is divider by 29
  • 30 MPLL input clock is divider by 30
  • 31 MPLL input clock is divider by 31
  • 32 MPLL input clock is divider by 32
  • 33 MPLL input clock is divider by 33
  • 34 MPLL input clock is divider by 34
  • 35 MPLL input clock is divider by 35
  • 36 MPLL input clock is divider by 36
  • 37 MPLL input clock is divider by 37
  • 38 MPLL input clock is divider by 38
  • 39 MPLL input clock is divider by 39
  • 40 MPLL input clock is divider by 40
  • 41 MPLL input clock is divider by 41
  • 42 MPLL input clock is divider by 42
  • 43 MPLL input clock is divider by 43
  • 44 MPLL input clock is divider by 44
  • 45 MPLL input clock is divider by 45
  • 46 MPLL input clock is divider by 46
  • 47 MPLL input clock is divider by 47
  • 48 MPLL input clock is divider by 48
  • 49 MPLL input clock is divider by 49
  • 50 MPLL input clock is divider by 50
  • 51 MPLL input clock is divider by 51
  • 52 MPLL input clock is divider by 52
  • 53 MPLL input clock is divider by 53
  • 54 MPLL input clock is divider by 54
  • 55 MPLL input clock is divider by 55
  • 56 MPLL input clock is divider by 56
  • 57 MPLL input clock is divider by 57
  • 58 MPLL input clock is divider by 58
  • 59 MPLL input clock is divider by 59
  • 60 MPLL input clock is divider by 60
  • 61 MPLL input clock is divider by 61
  • 62 MPLL input clock is divider by 62
  • 63 MPLL input clock is divider by 63
MPLLRDY31Memory PLL Status bit
  • 0 MPLL clock is not ready. Initializing DDR2 SDRAM when the clock is not ready will result in undefined behavior.
  • 1 MPLL clock is stable and is ready for use