The 14 registers of PORTD (I/O port D), from 0xBF860300, with their reset value and every field. The PIC32MZ2025DAL176 has 2254 registers in 102 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
PORTD I/O port D
ANSELD
Address
0xBF860300
Reset
0x0000C000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
ANSD15
15
ANSD14
14
TRISD
Address
0xBF860310
Reset
0x0000FEFF
Access
read/write
Size
32-bit
15 fields
Field
Bits
What it does
TRISD15
15
TRISD14
14
TRISD13
13
TRISD12
12
TRISD11
11
TRISD10
10
TRISD9
9
TRISD7
7
TRISD6
6
TRISD5
5
TRISD4
4
TRISD3
3
TRISD2
2
TRISD1
1
TRISD0
0
PORTD
Address
0xBF860320
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
Field
Bits
What it does
RD15
15
RD14
14
RD13
13
RD12
12
RD11
11
RD10
10
RD9
9
RD7
7
RD6
6
RD5
5
RD4
4
RD3
3
RD2
2
RD1
1
RD0
0
LATD
Address
0xBF860330
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
Field
Bits
What it does
LATD15
15
LATD14
14
LATD13
13
LATD12
12
LATD11
11
LATD10
10
LATD9
9
LATD7
7
LATD6
6
LATD5
5
LATD4
4
LATD3
3
LATD2
2
LATD1
1
LATD0
0
ODCD
Address
0xBF860340
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
Field
Bits
What it does
ODCD15
15
ODCD14
14
ODCD13
13
ODCD12
12
ODCD11
11
ODCD10
10
ODCD9
9
ODCD7
7
ODCD6
6
ODCD5
5
ODCD4
4
ODCD3
3
ODCD2
2
ODCD1
1
ODCD0
0
CNPUD
Address
0xBF860350
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
Field
Bits
What it does
CNPUD15
15
CNPUD14
14
CNPUD13
13
CNPUD12
12
CNPUD11
11
CNPUD10
10
CNPUD9
9
CNPUD7
7
CNPUD6
6
CNPUD5
5
CNPUD4
4
CNPUD3
3
CNPUD2
2
CNPUD1
1
CNPUD0
0
CNPDD
Address
0xBF860360
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
Field
Bits
What it does
CNPDD15
15
CNPDD14
14
CNPDD13
13
CNPDD12
12
CNPDD11
11
CNPDD10
10
CNPDD9
9
CNPDD7
7
CNPDD6
6
CNPDD5
5
CNPDD4
4
CNPDD3
3
CNPDD2
2
CNPDD1
1
CNPDD0
0
CNCONDChange Notice control for PORTx Register
Address
0xBF860370
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
ON
15
Change Notice Control ON bit
0 CN is disabled
1 CN is enabled
EDGEDETECT
11
Change Notification Style bit
0 Mismatch Style. Detect change from last PORTx read (CNSTATx used for CN Event).
1 Edge Style. Detect edge transitions (CNFx used for CN Event).