The 14 registers of PORTJ (I/O port J), from 0xBF860800, with their reset value and every field. The PIC32MZ2025DAS176 has 2318 registers in 103 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
PORTJ I/O port J
ANSELJ
Address
0xBF860800
Reset
0x00000004
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
ANSJ2
2
TRISJ
Address
0xBF860810
Reset
0x0000FFFF
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
TRISJ15
15
TRISJ14
14
TRISJ13
13
TRISJ12
12
TRISJ11
11
TRISJ10
10
TRISJ9
9
TRISJ8
8
TRISJ7
7
TRISJ6
6
TRISJ5
5
TRISJ4
4
TRISJ3
3
TRISJ2
2
TRISJ1
1
TRISJ0
0
PORTJ
Address
0xBF860820
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
RJ15
15
RJ14
14
RJ13
13
RJ12
12
RJ11
11
RJ10
10
RJ9
9
RJ8
8
RJ7
7
RJ6
6
RJ5
5
RJ4
4
RJ3
3
RJ2
2
RJ1
1
RJ0
0
LATJ
Address
0xBF860830
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
LATJ15
15
LATJ14
14
LATJ13
13
LATJ12
12
LATJ11
11
LATJ10
10
LATJ9
9
LATJ8
8
LATJ7
7
LATJ6
6
LATJ5
5
LATJ4
4
LATJ3
3
LATJ2
2
LATJ1
1
LATJ0
0
ODCJ
Address
0xBF860840
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
ODCJ15
15
ODCJ14
14
ODCJ13
13
ODCJ12
12
ODCJ11
11
ODCJ10
10
ODCJ9
9
ODCJ8
8
ODCJ7
7
ODCJ6
6
ODCJ5
5
ODCJ4
4
ODCJ3
3
ODCJ2
2
ODCJ1
1
ODCJ0
0
CNPUJ
Address
0xBF860850
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
CNPUJ15
15
CNPUJ14
14
CNPUJ13
13
CNPUJ12
12
CNPUJ11
11
CNPUJ10
10
CNPUJ9
9
CNPUJ8
8
CNPUJ7
7
CNPUJ6
6
CNPUJ5
5
CNPUJ4
4
CNPUJ3
3
CNPUJ2
2
CNPUJ1
1
CNPUJ0
0
CNPDJ
Address
0xBF860860
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
CNPDJ15
15
CNPDJ14
14
CNPDJ13
13
CNPDJ12
12
CNPDJ11
11
CNPDJ10
10
CNPDJ9
9
CNPDJ8
8
CNPDJ7
7
CNPDJ6
6
CNPDJ5
5
CNPDJ4
4
CNPDJ3
3
CNPDJ2
2
CNPDJ1
1
CNPDJ0
0
CNCONJChange Notice control for PORTx Register
Address
0xBF860870
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
ON
15
Change Notice Control ON bit
0 CN is disabled
1 CN is enabled
EDGEDETECT
11
Change Notification Style bit
0 Mismatch Style. Detect change from last PORTx read (CNSTATx used for CN Event).
1 Edge Style. Detect edge transitions (CNFx used for CN Event).
BETA