The 181 registers of CAN2 (CAN 2), from 0xBF881000, with their reset value and every field. The PIC32MZ2048EFH100 has 1618 registers in 90 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
CAN2 CAN 2
C2CONCAN Module Control Register
Address
0xBF881000
Reset
0x04800000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
ABAT
27
Abort All Pending Transmissions bit
0 Module will clear this bit when all transmissions aborted
1 Signal all transmit buffers to abort transmission
REQOP
26:24
Request Operation Mode bits
0 Set Normal Operation mode
1 Set Disable mode
2 Set Loopback mode
3 Set Listen Only mode
4 Set Configuration mode
5 Reserved - Do not use
6 Reserved - Do not use
7 Set Listen All Messages mode
OPMOD
23:21
Operation Mode Status bits
0 Module is in Normal Operation mode
1 Module is in Disable mode
2 Module is in Loopback mode
3 Module is in Listen Only mode
4 Module is in Configuration mode
5 Reserved
6 Reserved
7 Module is in Listen All Messages mode
CANCAP
20
CAN Message Receive Time Stamp Timer Capture Enable bit
0 Disable CAN message receive time stamp timer capture and stop CANTMR to conserve power
16 CANTMR value is stored on valid message reception and is stored with the message
ON
15
CAN On bit
0 CAN module is disabled
1 CAN module is enabled
SIDL
13
CANBUSY
11
CAN Module is Busy bit
0 The CAN module is completely disabled
1 The CAN module is active
DNCNT
4:0
Device Net Filter Bit Number bits
C2CFGCAN Baud Rate Configuration Register
Address
0xBF881010
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
WAKFIL
22
CAN Bus Line Filter Enable bit
0 CAN bus line filter is not used for wake-up
1 Use CAN bus line filter for wake-up
SEG2PH
18:16
Phase Buffer Segment 2 bits
0 Length is 1 x Tq
7 Length is 8 x Tq
SEG2PHTS
15
Phase Segment 2 Time Select bit
0 Maximum of SEG1PH or Information Processing Time
1 Freely programmable
SAM
14
Sample of the CAN Bus Line bit
0 Bus line is sampled once at the sample point
1 Bus line is sampled three times at the sample point
SEG1PH
13:11
Phase Buffer Segment 1 bits
0 Length is 1 x Tq
7 Length is 8 x Tq
PRSEG
10:8
Propagation Time Segment bits
0 Length is 1 x Tq
7 Length is 8 x Tq
SJW
7:6
Synchronization Jump Width bits
0 Length is 1 x Tq
1 Length is 2 x Tq
2 Length is 3 x Tq
3 Length is 4 x Tq
BRP
5:0
Baud Rate Prescaler bits
0 Tq = (2 x 1)/Tpbclk5
1 Tq = (2 x 2)/Tpbclk5
62 Tq = (2 x 63)/Tpbclk5
63 Tq = (2 x 64)/Tpbclk5
C2INTCAN Interrupt Register
Address
0xBF881020
Reset
0x00000000
Access
read/write
Size
32-bit
18 fields
Field
Bits
What it does
WAKIE
30
CAN Bus Activity Wake-up Interrupt Enable bit
0 Interrupt request is not enabled
1 Interrupt request is enabled
CERRIE
29
CAN Bus Error Interrupt Enable bit
0 Interrupt request is not enabled
1 Interrupt request is enabled
SERRIE
28
System Error Interrupt Enable bit
0 Interrupt request is not enabled
1 Interrupt request is enabled
RBOVIE
27
Receive Buffer Overflow Interrupt Enable bit
0 Interrupt request is not enabled
1 Interrupt request is enabled
MODIE
19
Mode Change Interrupt Enable bit
0 Interrupt request is not enabled
1 Interrupt request is enabled
CTMRIE
18
CAN Timestamp Timer Interrupt Enable bit
0 Interrupt request is not enabled
1 Interrupt request is enabled
RBIE
17
Receive Buffer Interrupt Enable bit
0 Interrupt request is not enabled
1 Interrupt request is enabled
TBIE
16
Transmit Buffer Interrupt Enable bit
0 Interrupt request is not enabled
1 Interrupt request is enabled
IVRIF
15
Invalid Message Received Interrupt Flag bit
0 An invalid message interrupt has not occurred
1 An invalid messages interrupt has occurred
WAKIF
14
CAN Bus Activity Wake-up Interrupt Flag bit
0 A bus wake-up activity interrupt has not occurred
1 A bus wake-up activity interrupt has occurred
CERRIF
13
CAN Bus Error Interrupt Flag bit
0 A CAN bus error has not occurred
1 A CAN bus error has occurred
SERRIF
12
System Error Interrupt Flag bit
0 A system error has not occurred
1 A system error occurred (typically an illegal address was presented to the System Bus)
RBOVIF
11
Receive Buffer Overflow Interrupt Flag bit
0 A receive buffer overflow has not occurred
1 A receive buffer overflow has occurred
MODIF
3
CAN Mode Change Interrupt Flag bit
0 A CAN module mode change has not occurred
1 A CAN module mode change has occurred (OPMOD has changed to reflect REQOP)
CTMRIF
2
CAN Timer Overflow Interrupt Flag bit
0 A CAN timer (CANTMR) overflow has not occurred
1 A CAN timer (CANTMR) overflow has occurred
RBIF
1
Receive Buffer Interrupt Flag bit
0 A receive buffer interrupt is not pending
1 A receive buffer interrupt is pending
TBIF
0
Transmit Buffer Interrupt Flag bit
0 A transmit buffer interrupt is not pending
1 A transmit buffer interrupt is pending
IVRIE
31
Invalid Message Received Interrupt Enable bit
0 Interrupt request is not enabled
1 Interrupt request is enabled
C2VECCAN Interrupt Code Register
Address
0xBF881030
Reset
0x00000040
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
FILHIT
12:8
Filter Hit Number bit
0 Filter 0
1 Filter 1
30 Filter 30
31 Filter 31
ICODE
6:0
Interrupt Flag Code bits
C2TRECCAN Transmit/Receive Error Count Register
Address
0xBF881040
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
Field
Bits
What it does
TXBO
21
TXBP
20
RXBP
19
TXWARN
18
RXWARN
17
EWARN
16
TERRCNT
15:8
RERRCNT
7:0
C2FSTATCAN FIFO Status Register
Address
0xBF881050
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
FIFOIP
31:0
FIFOx Interrupt Pending bits
0 No FIFO interrupts are pending
1 One or more enabled FIFO interrupts are pending
C2RXOVFCAN Receive FIFO Overflow Status Register
Address
0xBF881060
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
RXOVF
31:0
FIFOx Receive Overflow Interrupt Pending bit
0 FIFO has not overflowed
1 FIFO has overflowed
C2TMRCAN Timer Register
Address
0xBF881070
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
CANTSPRE
15:0
CAN Time Stamp Timer Prescaler bits
-1 CAN time stamp timer (CANTS) increments every 65,535 system clocks
0 CAN time stamp timer (CANTS) increments every system clock
CANTS
31:16
C2RXM0CAN Acceptance Filter Mask
Address
0xBF881080
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
MIDE
19
Identifier Receive Mode bit
0 Match either standard or extended address message if filters match (that is, if (Filter SID) = (Message SID) or if (FILTER SID/EID) = (Message SID/EID))
1 Match only message types (standard/extended address) that correspond to the EXID bit in filter
EID
17:0
Extended Identifier bits
0 Bit EIDx is dont care in filter operation
1 Include bit, EIDx, in filter comparison
SID
31:21
Standard Identifier bits
0 Bit SIDx is dont care in filter operation
1 Include bit, SIDx, in filter comparison
C2RXM1CAN Acceptance Filter Mask
Address
0xBF881090
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
MIDE
19
Identifier Receive Mode bit
0 Match either standard or extended address message if filters match (that is, if (Filter SID) = (Message SID) or if (FILTER SID/EID) = (Message SID/EID))
1 Match only message types (standard/extended address) that correspond to the EXID bit in filter
EID
17:0
Extended Identifier bits
0 Bit EIDx is dont care in filter operation
1 Include bit, EIDx, in filter comparison
SID
31:21
Standard Identifier bits
0 Bit SIDx is dont care in filter operation
1 Include bit, SIDx, in filter comparison
C2RXM2CAN Acceptance Filter Mask
Address
0xBF8810A0
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
MIDE
19
Identifier Receive Mode bit
0 Match either standard or extended address message if filters match (that is, if (Filter SID) = (Message SID) or if (FILTER SID/EID) = (Message SID/EID))
1 Match only message types (standard/extended address) that correspond to the EXID bit in filter
EID
17:0
Extended Identifier bits
0 Bit EIDx is dont care in filter operation
1 Include bit, EIDx, in filter comparison
SID
31:21
Standard Identifier bits
0 Bit SIDx is dont care in filter operation
1 Include bit, SIDx, in filter comparison
C2RXM3CAN Acceptance Filter Mask
Address
0xBF8810B0
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
MIDE
19
Identifier Receive Mode bit
0 Match either standard or extended address message if filters match (that is, if (Filter SID) = (Message SID) or if (FILTER SID/EID) = (Message SID/EID))
1 Match only message types (standard/extended address) that correspond to the EXID bit in filter
EID
17:0
Extended Identifier bits
0 Bit EIDx is dont care in filter operation
1 Include bit, EIDx, in filter comparison
SID
31:21
Standard Identifier bits
0 Bit SIDx is dont care in filter operation
1 Include bit, SIDx, in filter comparison
C2FLTCON0CAN Filter Control Register 0
Address
0xBF8810C0
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
MSEL3
30:29
Filter 3 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL3
28:24
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN2
23
Filter 2 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL2
22:21
Filter 2 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL2
20:16
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN1
15
Filter 1 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL1
14:13
Filter 1 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL1
12:8
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN0
7
Filter 0 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL0
6:5
Filter 0 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL0
4:0
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN3
31
Filter 3 Enable bit
0 Filter is disabled
1 Filter is enabled
C2FLTCON1CAN Filter Control Register 1
Address
0xBF8810D0
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
MSEL7
30:29
Filter 7 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL7
28:24
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN6
23
Filter 6 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL6
22:21
Filter 6 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL6
20:16
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN5
15
Filter 17 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL5
14:13
Filter 5 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL5
12:8
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN4
7
Filter 4 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL4
6:5
Filter 4 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL4
4:0
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN7
31
Filter 7 Enable bit
0 Filter is disabled
1 Filter is enabled
C2FLTCON2CAN Filter Control Register 2
Address
0xBF8810E0
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
MSEL11
30:29
Filter 11 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL11
28:24
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN10
23
Filter 10 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL10
22:21
Filter 10 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL10
20:16
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN9
15
Filter 9 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL9
14:13
Filter 9 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL9
12:8
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN8
7
Filter 8 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL8
6:5
Filter 8 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL8
4:0
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN11
31
Filter 11 Enable bit
0 Filter is disabled
1 Filter is enabled
C2FLTCON3CAN Filter Control Register 3
Address
0xBF8810F0
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
MSEL15
30:29
Filter 15 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL15
28:24
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN14
23
Filter 14 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL14
22:21
Filter 14 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL14
20:16
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN13
15
Filter 13 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL13
14:13
Filter 13 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL13
12:8
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN12
7
Filter 12 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL12
6:5
Filter 12 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL12
4:0
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN15
31
Filter 15 Enable bit
0 Filter is disabled
1 Filter is enabled
C2FLTCON4CAN Filter Control Register 4
Address
0xBF881100
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
MSEL19
30:29
Filter 19 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL19
28:24
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN18
23
Filter 18 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL18
22:21
Filter 18 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL18
20:16
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN17
15
Filter 13 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL17
14:13
Filter 17 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL17
12:8
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN16
7
Filter 16 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL16
6:5
Filter 16 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL16
4:0
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN19
31
Filter 19 Enable bit
0 Filter is disabled
1 Filter is enabled
C2FLTCON5CAN Filter Control Register 5
Address
0xBF881110
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
MSEL23
30:29
Filter 23 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL23
28:24
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN22
23
Filter 22 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL22
22:21
Filter 22 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL22
20:16
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN21
15
Filter 21 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL21
14:13
Filter 21 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL21
12:8
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN20
7
Filter 20 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL20
6:5
Filter 20 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL20
4:0
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN23
31
Filter 23 Enable bit
0 Filter is disabled
1 Filter is enabled
C2FLTCON6CAN Filter Control Register 6
Address
0xBF881120
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
MSEL27
30:29
Filter 27 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL27
28:24
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN26
23
Filter 26 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL26
22:21
Filter 26 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL26
20:16
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN25
15
Filter 25 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL25
14:13
Filter 25 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL25
12:8
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN24
7
Filter 24 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL24
6:5
Filter 24 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL24
4:0
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN27
31
Filter 27 Enable bit
0 Filter is disabled
1 Filter is enabled
C2FLTCON7CAN Filter Control Register 7
Address
0xBF881130
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
MSEL31
30:29
Filter 31 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL31
28:24
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN30
23
Filter 30Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL30
22:21
Filter 30Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL30
20:16
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN29
15
Filter 29 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL29
14:13
Filter 29 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL29
12:8
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN28
7
Filter 28 Enable bit
0 Filter is disabled
1 Filter is enabled
MSEL28
6:5
Filter 28 Mask Select bits
0 Acceptance Mask 0 selected
1 Acceptance Mask 1 selected
2 Acceptance Mask 2 selected
3 Acceptance Mask 3 selected
FSEL28
4:0
FIFO Selection bits
0 Message matching filter is stored in FIFO buffer 0
1 Message matching filter is stored in FIFO buffer 1
2 Message matching filter is stored in FIFO buffer 2
3 Message matching filter is stored in FIFO buffer 3
4 Message matching filter is stored in FIFO buffer 4
5 Message matching filter is stored in FIFO buffer 5
6 Message matching filter is stored in FIFO buffer 6
7 Message matching filter is stored in FIFO buffer 7
8 Message matching filter is stored in FIFO buffer 8
9 Message matching filter is stored in FIFO buffer 9
10 Message matching filter is stored in FIFO buffer 10
11 Message matching filter is stored in FIFO buffer 11
12 Message matching filter is stored in FIFO buffer 12
13 Message matching filter is stored in FIFO buffer 13
14 Message matching filter is stored in FIFO buffer 14
15 Message matching filter is stored in FIFO buffer 15
16 Message matching filter is stored in FIFO buffer 16
17 Message matching filter is stored in FIFO buffer 17
18 Message matching filter is stored in FIFO buffer 18
19 Message matching filter is stored in FIFO buffer 19
20 Message matching filter is stored in FIFO buffer 20
21 Message matching filter is stored in FIFO buffer 21
22 Message matching filter is stored in FIFO buffer 22
23 Message matching filter is stored in FIFO buffer 23
24 Message matching filter is stored in FIFO buffer 24
25 Message matching filter is stored in FIFO buffer 25
26 Message matching filter is stored in FIFO buffer 26
27 Message matching filter is stored in FIFO buffer 27
28 Message matching filter is stored in FIFO buffer 28
29 Message matching filter is stored in FIFO buffer 29
30 Message matching filter is stored in FIFO buffer 30
31 Message matching filter is stored in FIFO buffer 31
FLTEN31
31
Filter 31 Enable bit
0 Filter is disabled
1 Filter is enabled
C2RXF0CAN Acceptance Filter
Address
0xBF881140
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF1CAN Acceptance Filter
Address
0xBF881150
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF2CAN Acceptance Filter
Address
0xBF881160
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF3CAN Acceptance Filter
Address
0xBF881170
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF4CAN Acceptance Filter
Address
0xBF881180
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF5CAN Acceptance Filter
Address
0xBF881190
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF6CAN Acceptance Filter
Address
0xBF8811A0
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF7CAN Acceptance Filter
Address
0xBF8811B0
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF8CAN Acceptance Filter
Address
0xBF8811C0
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF9CAN Acceptance Filter
Address
0xBF8811D0
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF10CAN Acceptance Filter
Address
0xBF8811E0
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF11CAN Acceptance Filter
Address
0xBF8811F0
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF12CAN Acceptance Filter
Address
0xBF881200
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF13CAN Acceptance Filter
Address
0xBF881210
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF14CAN Acceptance Filter
Address
0xBF881220
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF15CAN Acceptance Filter
Address
0xBF881230
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF16CAN Acceptance Filter
Address
0xBF881240
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF17CAN Acceptance Filter
Address
0xBF881250
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF18CAN Acceptance Filter
Address
0xBF881260
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF19CAN Acceptance Filter
Address
0xBF881270
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF20CAN Acceptance Filter
Address
0xBF881280
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF21CAN Acceptance Filter
Address
0xBF881290
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF22CAN Acceptance Filter
Address
0xBF8812A0
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF23CAN Acceptance Filter
Address
0xBF8812B0
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF24CAN Acceptance Filter
Address
0xBF8812C0
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF25CAN Acceptance Filter
Address
0xBF8812D0
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF26CAN Acceptance Filter
Address
0xBF8812E0
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF27CAN Acceptance Filter
Address
0xBF8812F0
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF28CAN Acceptance Filter
Address
0xBF881300
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF29CAN Acceptance Filter
Address
0xBF881310
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF30CAN Acceptance Filter
Address
0xBF881320
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2RXF31CAN Acceptance Filter
Address
0xBF881330
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
EXID
19
Extended Identifier Enable bits
0 Match only messages with standard identifier addresses
1 Match only messages with extended identifier addresses
EID
17:0
Extended Identifier bits
0 Message address bit EIDx must be 0 to match filter
1 Message address bit EIDx must be 1 to match filter
SID
31:21
Standard Identifier bits
0 Message address bit SIDx must be 0 to match filter
1 Message address bit SIDx must be 1 to match filter
C2FIFOBACAN Message Buffer Base Address Register
Address
0xBF881340
Reset
0x00000000
Access
read/write
Size
32-bit
C2FIFOCON0CAN FIFO Control Register
Address
0xBF881350
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT0CAN FIFO Interrupt Register
Address
0xBF881360
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA0CAN FIFO User Address Register
Address
0xBF881370
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI0CAN Module Message Index Register
Address
0xBF881380
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON1CAN FIFO Control Register
Address
0xBF881390
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT1CAN FIFO Interrupt Register
Address
0xBF8813A0
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA1CAN FIFO User Address Register
Address
0xBF8813B0
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI1CAN Module Message Index Register
Address
0xBF8813C0
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON2CAN FIFO Control Register
Address
0xBF8813D0
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT2CAN FIFO Interrupt Register
Address
0xBF8813E0
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA2CAN FIFO User Address Register
Address
0xBF8813F0
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI2CAN Module Message Index Register
Address
0xBF881400
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON3CAN FIFO Control Register
Address
0xBF881410
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT3CAN FIFO Interrupt Register
Address
0xBF881420
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA3CAN FIFO User Address Register
Address
0xBF881430
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI3CAN Module Message Index Register
Address
0xBF881440
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON4CAN FIFO Control Register
Address
0xBF881450
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT4CAN FIFO Interrupt Register
Address
0xBF881460
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA4CAN FIFO User Address Register
Address
0xBF881470
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI4CAN Module Message Index Register
Address
0xBF881480
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON5CAN FIFO Control Register
Address
0xBF881490
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT5CAN FIFO Interrupt Register
Address
0xBF8814A0
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA5CAN FIFO User Address Register
Address
0xBF8814B0
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI5CAN Module Message Index Register
Address
0xBF8814C0
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON6CAN FIFO Control Register
Address
0xBF8814D0
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT6CAN FIFO Interrupt Register
Address
0xBF8814E0
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA6CAN FIFO User Address Register
Address
0xBF8814F0
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI6CAN Module Message Index Register
Address
0xBF881500
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON7CAN FIFO Control Register
Address
0xBF881510
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT7CAN FIFO Interrupt Register
Address
0xBF881520
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA7CAN FIFO User Address Register
Address
0xBF881530
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI7CAN Module Message Index Register
Address
0xBF881540
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON8CAN FIFO Control Register
Address
0xBF881550
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT8CAN FIFO Interrupt Register
Address
0xBF881560
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA8CAN FIFO User Address Register
Address
0xBF881570
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI8CAN Module Message Index Register
Address
0xBF881580
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON9CAN FIFO Control Register
Address
0xBF881590
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT9CAN FIFO Interrupt Register
Address
0xBF8815A0
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA9CAN FIFO User Address Register
Address
0xBF8815B0
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI9CAN Module Message Index Register
Address
0xBF8815C0
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON10CAN FIFO Control Register
Address
0xBF8815D0
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT10CAN FIFO Interrupt Register
Address
0xBF8815E0
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA10CAN FIFO User Address Register
Address
0xBF8815F0
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI10CAN Module Message Index Register
Address
0xBF881600
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON11CAN FIFO Control Register
Address
0xBF881610
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT11CAN FIFO Interrupt Register
Address
0xBF881620
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA11CAN FIFO User Address Register
Address
0xBF881630
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI11CAN Module Message Index Register
Address
0xBF881640
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON12CAN FIFO Control Register
Address
0xBF881650
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT12CAN FIFO Interrupt Register
Address
0xBF881660
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA12CAN FIFO User Address Register
Address
0xBF881670
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI12CAN Module Message Index Register
Address
0xBF881680
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON13CAN FIFO Control Register
Address
0xBF881690
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT13CAN FIFO Interrupt Register
Address
0xBF8816A0
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA13CAN FIFO User Address Register
Address
0xBF8816B0
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI13CAN Module Message Index Register
Address
0xBF8816C0
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON14CAN FIFO Control Register
Address
0xBF8816D0
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT14CAN FIFO Interrupt Register
Address
0xBF8816E0
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA14CAN FIFO User Address Register
Address
0xBF8816F0
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI14CAN Module Message Index Register
Address
0xBF881700
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON15CAN FIFO Control Register
Address
0xBF881710
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT15CAN FIFO Interrupt Register
Address
0xBF881720
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA15CAN FIFO User Address Register
Address
0xBF881730
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI15CAN Module Message Index Register
Address
0xBF881740
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON16CAN FIFO Control Register
Address
0xBF881750
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT16CAN FIFO Interrupt Register
Address
0xBF881760
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA16CAN FIFO User Address Register
Address
0xBF881770
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI16CAN Module Message Index Register
Address
0xBF881780
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON17CAN FIFO Control Register
Address
0xBF881790
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT17CAN FIFO Interrupt Register
Address
0xBF8817A0
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA17CAN FIFO User Address Register
Address
0xBF8817B0
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI17CAN Module Message Index Register
Address
0xBF8817C0
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON18CAN FIFO Control Register
Address
0xBF8817D0
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT18CAN FIFO Interrupt Register
Address
0xBF8817E0
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA18CAN FIFO User Address Register
Address
0xBF8817F0
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI18CAN Module Message Index Register
Address
0xBF881800
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON19CAN FIFO Control Register
Address
0xBF881810
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT19CAN FIFO Interrupt Register
Address
0xBF881820
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA19CAN FIFO User Address Register
Address
0xBF881830
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI19CAN Module Message Index Register
Address
0xBF881840
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON20CAN FIFO Control Register
Address
0xBF881850
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT20CAN FIFO Interrupt Register
Address
0xBF881860
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA20CAN FIFO User Address Register
Address
0xBF881870
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI20CAN Module Message Index Register
Address
0xBF881880
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON21CAN FIFO Control Register
Address
0xBF881890
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT21CAN FIFO Interrupt Register
Address
0xBF8818A0
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA21CAN FIFO User Address Register
Address
0xBF8818B0
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI21CAN Module Message Index Register
Address
0xBF8818C0
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON22CAN FIFO Control Register
Address
0xBF8818D0
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT22CAN FIFO Interrupt Register
Address
0xBF8818E0
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA22CAN FIFO User Address Register
Address
0xBF8818F0
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI22CAN Module Message Index Register
Address
0xBF881900
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON23CAN FIFO Control Register
Address
0xBF881910
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT23CAN FIFO Interrupt Register
Address
0xBF881920
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA23CAN FIFO User Address Register
Address
0xBF881930
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI23CAN Module Message Index Register
Address
0xBF881940
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON24CAN FIFO Control Register
Address
0xBF881950
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT24CAN FIFO Interrupt Register
Address
0xBF881960
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA24CAN FIFO User Address Register
Address
0xBF881970
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI24CAN Module Message Index Register
Address
0xBF881980
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON25CAN FIFO Control Register
Address
0xBF881990
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT25CAN FIFO Interrupt Register
Address
0xBF8819A0
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA25CAN FIFO User Address Register
Address
0xBF8819B0
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI25CAN Module Message Index Register
Address
0xBF8819C0
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON26CAN FIFO Control Register
Address
0xBF8819D0
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT26CAN FIFO Interrupt Register
Address
0xBF8819E0
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA26CAN FIFO User Address Register
Address
0xBF8819F0
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI26CAN Module Message Index Register
Address
0xBF881A00
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON27CAN FIFO Control Register
Address
0xBF881A10
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT27CAN FIFO Interrupt Register
Address
0xBF881A20
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA27CAN FIFO User Address Register
Address
0xBF881A30
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI27CAN Module Message Index Register
Address
0xBF881A40
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON28CAN FIFO Control Register
Address
0xBF881A50
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT28CAN FIFO Interrupt Register
Address
0xBF881A60
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA28CAN FIFO User Address Register
Address
0xBF881A70
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI28CAN Module Message Index Register
Address
0xBF881A80
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON29CAN FIFO Control Register
Address
0xBF881A90
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT29CAN FIFO Interrupt Register
Address
0xBF881AA0
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA29CAN FIFO User Address Register
Address
0xBF881AB0
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI29CAN Module Message Index Register
Address
0xBF881AC0
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON30CAN FIFO Control Register
Address
0xBF881AD0
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT30CAN FIFO Interrupt Register
Address
0xBF881AE0
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
C2FIFOUA30CAN FIFO User Address Register
Address
0xBF881AF0
Reset
0x00000000
Access
read only
Size
32-bit
C2FIFOCI30CAN Module Message Index Register
Address
0xBF881B00
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CFIFOCI
4:0
C2FIFOCON31CAN FIFO Control Register
Address
0xBF881B10
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FSIZE
20:16
FIFO Size bits(1)
0 FIFO is 1 message deep
1 FIFO is 2 messages deep
2 FIFO is 3 messages deep
31 FIFO is 32 messages deep
FRESET
14
FIFO Reset bits
0 No effect
1 FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
UINC
13
Increment Head/Tail bit
0 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message
0 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
DONLY
12
Store Message Data Only bit(1)
0 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
0 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO, 0 = Full message is stored, including identifier
TXEN
7
TX/RX Buffer Selection bit
0 FIFO is a Receive FIFO
1 FIFO is a Transmit FIFO
TXABAT
6
Message Aborted bit(2)
0 Message completed successfully
1 Message was aborted
TXLARB
5
Message Lost Arbitration bit(3)
0 Message did not lose arbitration while being sent
1 Message lost arbitration while being sent
TXERR
4
Error Detected During Transmission bit(3)
0 A bus error did not occur while the message was being sent
1 A bus error occurred while the message was being sent
TXREQ
3
Message Send Request
0 1: (FIFO configured as a Transmit FIFO) Setting this bit to 1 requests sending a message. The bit will automatically clear when all the messages queued in the FIFO are successfully sent. Clearing the bit to 0 while set (1) will request a message abort.
0 0: (FIFO configured as a Receive FIFO) This bit has no effect.
RTREN
2
Auto RTR Enable bit
0 When a remote transmit is received, TXREQ will be unaffected
1 When a remote transmit is received, TXREQ will be set
TXPRI
1:0
Message Transmit Priority bits
0 Lowest Message Priority
1 Low Intermediate Message Priority
2 High Intermediate Message Priority
3 Highest Message Priority
C2FIFOINT31CAN FIFO Interrupt Register
Address
0xBF881B20
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
TXNFULLIE
26
Transmit FIFO Not Full Interrupt Enable bit
0 Interrupt disabled for FIFO not full
1 Interrupt enabled for FIFO not full
TXHALFIE
25
Transmit FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
TXEMPTYIE
24
Transmit FIFO Empty Interrupt Enable bit
0 Interrupt disabled for FIFO empty
1 Interrupt enabled for FIFO empty
RXOVFLIE
19
Overflow Interrupt Enable bit
0 Interrupt disabled for overflow event
1 Interrupt enabled for overflow event
RXFULLIE
18
Full Interrupt Enable bit
0 Interrupt disabled for FIFO full
1 Interrupt enabled for FIFO full
RXHALFIE
17
FIFO Half Full Interrupt Enable bit
0 Interrupt disabled for FIFO half full
1 Interrupt enabled for FIFO half full
RXNEMPTYIE
16
Empty Interrupt Enable bit
0 Interrupt disabled for FIFO not empty
1 Interrupt enabled for FIFO not empty
TXNFULLIF
10
Transmit FIFO Not Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full, 0 = FIFO is full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXHALFIF
9
FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is ? half full, 0 = FIFO is > half full
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
TXEMPTYIF
8
Transmit FIFO Empty Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is empty, 0 = FIFO is not empty, at least 1 message queued to be transmitted
0 0: (FIFO configured as a Receive Buffer) Unused, reads 0
RXOVFLIF
3
Receive FIFO Overflow Interrupt Flag bit
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred, 0 = No overflow event occurred
RXFULLIF
2
Receive FIFO Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is full, 0 = FIFO is not full
RXHALFIF
1
Receive FIFO Half Full Interrupt Flag bit(1)
0 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is ? half full, 0 = FIFO is < half full
RXNEMPTYIF
0
Receive Buffer Not Empty Interrupt Flag bit(1)
0 0: (FIFO configured as a Receive Buffer) 1 = FIFO is not empty, has at least 1 message, 0 = FIFO is empty
1 1: (FIFO configured as a Transmit Buffer) Unused, reads 0
BETA