PIC32MZ2048EFH100 PCACHE registers

The 2 registers of PCACHE (Prefetch cache), from 0xBF8E0000, with their reset value and every field. The PIC32MZ2048EFH100 has 1618 registers in 90 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

PCACHE Prefetch cache

PRECONPrefetch Module Control Register

Address
0xBF8E0000
Reset
0x00000007
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
PFMSECEN26Flash SEC Interrupt Enable bit
  • 0 Do not generate an interrupt when the PFMSEC bit is set
  • 1 Generate an interrupt when the PFMSEC bit (PRESTAT) is set
PREFEN5:4Predictive Prefetch Enable bits
  • 0 Disable predictive prefetch
  • 1 Enable predictive prefetch for CPU instructions only
  • 2 Enable predictive prefetch for CPU instructions and CPU data
  • 3 Enable predictive prefetch for any address
PFMWS2:0PFM Access Time Defined in Terms of SYSCLK Wait States bits
  • 0 Zero Wait states
  • 1 One Wait state
  • 2 Two Wait states
  • 3 Three Wait states
  • 4 Four Wait states
  • 5 Five Wait states
  • 6 Six Wait states
  • 7 Seven Wait states

PRESTATPrefetch Module Status Register

Address
0xBF8E0010
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
PFMDED27Flash Double-bit Error Detected Status bit
  • 0 A DED error has not occurred
  • 1 A DED error has occurred
PFMSEC26Flash Single-bit Error Corrected Status bit
  • 0 A SEC error has not occurred
  • 1 A SEC error occurred when PFMSECCNT was equal to zero
PFMSECCNT7:0Flash SEC Count bits
  • 0 SEC count of 0
  • 1 SEC count of 1
  • 254 SEC count of 254
  • 255 SEC count of 255