PIC32MZ2048EFM124 CRYPTO registers

The 10 registers of CRYPTO (Crypto engine), from 0xBF8E5000, with their reset value and every field. The PIC32MZ2048EFM124 has 1675 registers in 93 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

CRYPTO Crypto engine

CEVERCrypto Engine Revision

Address
0xBF8E5000
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
FieldBitsWhat it does
VERSION23:16
ID15:0
REVISION31:24

CECONCrypto Engine Control Register

Address
0xBF8E5004
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
SWAPOEN7Swap Output Data Enable bit
  • 0 Output data is not byte swapped when written by dedicated DMA
  • 1 Output data is byte swapped when written by dedicated DMA
SWRST6Software Reset bit
  • 0 Normal operation
  • 1 Initiate a software reset of the Crypto Engine
SWAPEN5Input Data Swap Enable bit
  • 0 Input data is not byte swapped when read by dedicated DMA
  • 1 Input data is byte swapped when read by dedicated DMA
BDPCHST2Buffer Descriptor Processor Fetch Enable bit
  • 0 BDP descriptor fetch is disabled
  • 1 BDP descriptor fetch is enabled
BDPPLEN1Buffer Descriptor Processor Poll Enable bit
  • 0 Do not poll
  • 1 Poll for descriptor until valid bit is set
DMAEN0DMA Enable bit
  • 0 Crypto Engine DMA is disabled
  • 1 Crypto Engine DMA is enabled

CEBDADDRCrypto Engine Buffer Descriptor Register

Address
0xBF8E5008
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
BDPADDR31:0

CEBDPADDRCrypto Engine Buffer Descriptor Processor Register

Address
0xBF8E500C
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
BASEADDR31:0

CESTATCrypto Engine Status Register

Address
0xBF8E5010
Reset
0x00000000
Access
read only
Size
32-bit
7 fields
FieldBitsWhat it does
ERROP28:26Internal Error Operation Status bits
  • 0 Reserved
  • 1 Encryption
  • 2 Decryption
  • 3 Reserved
  • 4 Authentication
  • 5 Reserved
  • 6 Reserved
  • 7 Reserved
ERRPHASE25:24Internal Error Phase of DMA Status bits
  • 0 Buffer Descriptor (BD) access
  • 1 Security Association (SA) access
  • 2 Source data
  • 3 Destination data
BDSTATE21:18Buffer Descriptor Processor State Status bits
  • 0 BDP is idle
  • 1 Descriptor fetch request is pending
  • 2 BDP is loading
  • 3 Data phase
  • 4 Descriptor is done
  • 5 Fetch BDP is disabled
  • 6 SA fetch
  • 7 Reserved
  • 8 Reserved
  • 9 Reserved
  • 10 Reserved
  • 11 Reserved
  • 12 Reserved
  • 13 Reserved
  • 14 Reserved
  • 15 Reserved
START17DMA Start Status bit
  • 0 DMA start has not occurred
  • 1 DMA start has occurred
ACTIVE16Buffer Descriptor Processor Status bit
  • 0 BDP is idle
  • 1 BDP is active
BDCTRL15:0
ERRMODE31:29Internal Error Mode Status bits
  • 0 Normal operation
  • 1 Preboot authentication
  • 2 KEK operation
  • 3 CEK operation
  • 4 Reserved
  • 5 Reserved
  • 6 Reserved
  • 7 Reserved

CEINTSRCCrypto Engine Interrupt Source Register

Address
0xBF8E5014
Reset
0x00000000
Access
read only
Size
32-bit
4 fields
FieldBitsWhat it does
AREIF3Access Response Error Interrupt bit
  • 0 No error has occurred
  • 1 Error occurred trying to access memory outside the Crypto Engine
PKTIF2DMA Packet Completion Interrupt Status bit
  • 0 DMA packet was not completed
  • 1 DMA packet was completed
CBDIF1BD Transmit Status bit
  • 0 Last BD transmit has not been processed
  • 1 Last BD transmit was processed
PENDIF0Crypto Engine Interrupt Pending Status bit
  • 0 Crypto Engine interrupt is not pending
  • 1 Crypto Engine interrupt is pending (this value is the result of an OR of all interrupts in the Crypto Engine)

CEINTENCrypto Engine Interrupt Enable Register

Address
0xBF8E5018
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
AREIE3Access Response Error Interrupt Enable bit
  • 0 Access response error interrupts are not enabled
  • 1 Access response error interrupts are enabled
PKTIE2DMA Packet Completion Interrupt Enable bit
  • 0 DMA packet completion interrupts are not enabled
  • 1 DMA packet completion interrupts are enabled
CBDIE1
PENDIE0Master Interrupt Enable bit
  • 0 Crypto Engine interrupts are not enabled
  • 1 Crypto Engine interrupts are enabled

CEPOLLCONCrypto Engine Poll Control Register

Address
0xBF8E501C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
BDPPLCON15:0

CEHDLENCrypto Engine Header Length Register

Address
0xBF8E5020
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
HDRLEN7:0

CETRLLENCrypto Engine Trailer Length Register

Address
0xBF8E5024
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TRLRLEN7:0