The 11 registers of PORTK (I/O port K), from 0xBF860910, with their reset value and every field. The PIC32MZ2048EFM144 has 1692 registers in 94 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
PORTK I/O port K
TRISK
Address
0xBF860910
Reset
0x000000FF
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
TRISK7
7
TRISK6
6
TRISK5
5
TRISK4
4
TRISK3
3
TRISK2
2
TRISK1
1
TRISK0
0
PORTK
Address
0xBF860920
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
RK7
7
RK6
6
RK5
5
RK4
4
RK3
3
RK2
2
RK1
1
RK0
0
LATK
Address
0xBF860930
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
LATK7
7
LATK6
6
LATK5
5
LATK4
4
LATK3
3
LATK2
2
LATK1
1
LATK0
0
ODCK
Address
0xBF860940
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
ODCK7
7
ODCK6
6
ODCK5
5
ODCK4
4
ODCK3
3
ODCK2
2
ODCK1
1
ODCK0
0
CNPUK
Address
0xBF860950
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
CNPUK7
7
CNPUK6
6
CNPUK5
5
CNPUK4
4
CNPUK3
3
CNPUK2
2
CNPUK1
1
CNPUK0
0
CNPDK
Address
0xBF860960
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
CNPDK7
7
CNPDK6
6
CNPDK5
5
CNPDK4
4
CNPDK3
3
CNPDK2
2
CNPDK1
1
CNPDK0
0
CNCONKChange Notice control for PORTx Register
Address
0xBF860970
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
ON
15
Change Notice Control ON bit
0 CN is disabled
1 CN is enabled
EDGEDETECT
11
Change Notification Style bit
0 Mismatch Style. Detect change from last PORTx read (CNSTATx used for CN Event).
1 Edge Style. Detect edge transitions (CNFx used for CN Event).
BETA