PIC32MZ2064DAR176 SDHC registers

The 16 registers of SDHC (SD host controller), from 0xBF8EC004, with their reset value and every field. The PIC32MZ2064DAR176 has 2308 registers in 102 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

SDHC SD host controller

SDHCBLKCONSDHC Block Control Register

Address
0xBF8EC004
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
BLKSIZE9:0
BLKCNT31:16

SDHCARGSDHC Argument Register

Address
0xBF8EC008
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ARG31:0

SDHCMODESDHC Mode Register

Address
0xBF8EC00C
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
CIDX29:24
CTYPE23:22Command Type bits
  • 0 Normal
  • 1 Suspend
  • 2 Resume
  • 3 Abort
DPRESSEL21
CIDXCEN20Command Index Check Enable bit
  • 0 Command index check is disabled
  • 1 Command index check is enabled
CCRCCEN19Command CRC Check Enable bit
  • 0 Command CRC check is disabled
  • 1 Command CRC check is enabled
RESPTYPE17:16Response Type Select bits
  • 0 No response
  • 1 Response length 136
  • 2 Response length 48
  • 3 Response length 48; check busy after response
BSEL5Multiple/Single Block Select bit
  • 0 Single block
  • 1 Multiple block, set when issuing multiple transfer commands using DAT lines
DTXDIRSEL4
ACEN3:2Auto CMD12 Enable bits
  • 0 Auto CMD 12 is disabled
  • 1 Auto CMD12 is enabled
  • 2 Reserved
  • 3 Reserved
BCEN1Block Count Enable Bit
  • 0 Block count is disabled
  • 1 Block count is enabled
DMAEN0DMA Enable bit
  • 0 CPU is used to transfer data
  • 1 DMA (ADMA) is used to transfer data

SDHCDATASDHC Data Register

Address
0xBF8EC020
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

SDHCSTAT1SDHC Status Register 1

Address
0xBF8EC024
Reset
0x00000000
Access
read only
Size
32-bit
16 fields
FieldBitsWhat it does
CMDSLVL24Command Line Signal Level bit
  • 0 CMD line is low
  • 1 CMD line is high
DATA3SLVL23DATA3 Signal Level bit
  • 0 DAT3 line is low
  • 1 DAT3 line is high
DATA2SLVL22DATA2 Signal Level bit
  • 0 DAT2 line is low
  • 1 DAT2 line is high
DATA1SLVL21DATA1 Signal Level bit
  • 0 DAT1 line is low
  • 1 DAT1 line is high
DATA0SLVL20DATA0 Signal Level bit
  • 0 DAT0 line is low
  • 1 DAT0 line is high
WPSLVL19Write-protect Signal Level bit
  • 0 Write-protect is enabled
  • 1 Write-protect is disabled
CDSLVL18Card Detect Signal Level bit
  • 0 Card is not present
  • 1 Card is present
CARDST17Card State Stable bit
  • 0 Reset or debouncing
  • 1 No card or inserted
CARDINS16Card Inserted bit
  • 0 Reset or debouncing or no card
  • 1 Card inserted
BREN11Buffer Read Enable bit
  • 0 Buffer read is disabled
  • 1 Buffer read is enabled
BWEN10Buffer Write Enable bit
  • 0 Buffer write is disabled
  • 1 Buffer write is enabled
RDACTIVE9Read Transfer Active bit
  • 0 No valid data
  • 1 Data is being transferred
WRACTIVE8Write Transfer Active bit
  • 0 No valid data
  • 1 Data is being transferred
DLACTIVE2DAT Line Active bit
  • 0 DAT line is inactive
  • 1 DAT line is active
CINHDAT1Command Inhibit bit (DAT) bit
  • 0 A command that uses the DAT line can be issued
  • 1 A command that uses the DAT line cannot be issued
CINHCMD0Command Inhibit bit (CMD) bit
  • 0 A command can only be issued using the CMD line
  • 1 A command cannot be issued

SDHCCON1SDHC Control Register 1

Address
0xBF8EC028
Reset
0x00000000
Access
read/write
Size
32-bit
13 fields
FieldBitsWhat it does
WKONREM26Wake-up Event Enable on SD Card Removal bit
  • 0 Wake-up event is disabled
  • 1 Wake-up event is enabled
WKONINS25Wake-up Event Enable on SD Card Insertion bit
  • 0 Wake-up event is disabled
  • 1 Wake-up event is enabled
WKONINT24Wake-up Event Enable on SD Card Interrupt bit
  • 0 Wake-up event is disabled
  • 1 Wake-up event is enabled
INTBG19Interrupt at Block Gap bit
  • 0 Interrupt is disabled
  • 1 Interrupt is enabled
RDWTCON18Read Wait Control bit
  • 0 Read wait control is disabled
  • 1 Read wait control is enabled
CONTREQ17Continue Request bit
  • 0 No effect
  • 1 Restart
SBGREQ16Stop at Block Gap Request bit
  • 0 Transfer
  • 1 Stop
SDBP8SD Bus Power bit
  • 0 Bus power is off
  • 1 Bus power is on
CDSSEL7Card Detect Signal Selection bit
  • 0 SDCDx is selected (for normal use)
  • 1 The card detect test level is select (for test purposes)
CDTLVL6Card Detect Test Level bit
  • 0 Card is not inserted
  • 1 Card is inserted
DMASEL4:3DMA Select bits
  • 0 Reserved
  • 1 Reserved
  • 2 32-bit address ADMA2 is selected
  • 3 Reserved
HSEN2High-Speed Enable bit
  • 0 Normal Speed mode is enabled
  • 1 High-Speed mode is enabled
DTXWIDTH1Data Transfer Width bit
  • 0 1-bit mode
  • 1 4-bit mode

SDHCCON2SDHC Control Register 2

Address
0xBF8EC02C
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
SWRDAT26
SWRCMD25Software Reset for CMD Line bit
  • 0 Continue operation
  • 1 Clears Present State and Interrupt Status registers and CMD bits
SWRALL24Software Reset for All bit
  • 0 Divided Clock mode is selected
  • 1 Issue reset command and reinitialize the SD card
DTOC19:16Data Time-out Counter Value bits
  • 0 Time-out clock x 213
  • 1 Time-out clock x 214
  • 14 Time-out clock x 227
  • 15 Reserved
SDCLKDIV15:8
SDCLKEN2SD Clock Enable bit
  • 0 SD clock is disabled
  • 1 SD clock is enabled
ICLKSTABLE1Internal Clock Stable bit
  • 0 Internal clock is not ready
  • 1 Internal clock is ready
ICLKEN0Internal Clock Enable bit
  • 0 Stop
  • 1 Oscillate

SDHCINTSTATSDHC Interrupt Status Register

Address
0xBF8EC030
Reset
0x03FF81FF
Access
read only
Size
32-bit
20 fields
FieldBitsWhat it does
ADEIF25ADMA Error Interrupt Flag bit
  • 0 ADMA error has not occurred
  • 1 ADMA error has occurred
ACEIF24Auto CMD12 Error Interrupt Flag bit
  • 0 Auto CMD12 error has not occurred
  • 1 Auto CMD12 error has occurred
CLEIF23Current-Limit Error Interrupt Flag bit
  • 0 Current-limit error has not occurred
  • 1 Current-limit error has occurred
DEBEIF22Data End Bit Error Interrupt Flag bit
  • 0 Data End bit error has not occurred
  • 1 Data End bit error has occurred
DCRCEIF21Data CRC Error Interrupt Flag bit
  • 0 Data CRC error has not occurred
  • 1 Data CRC error has occurred
DTOEIF20Data Time-out Error Interrupt Flag bit
  • 0 Data time-out error has not occurred
  • 1 Data time-out error has occurred
CIDXEIF19Command Index Error Interrupt Flag bit
  • 0 Command index error has not occurred
  • 1 Command index error has occurred
CEBEIF18Command End Bit Error Interrupt Flag bit
  • 0 End bit error was not generated
  • 1 End bit error was generated
CCRCEIF17Command CRC Error Interrupt Flag bit
  • 0 Command CRC error has not occurred
  • 1 Command CRC error has occurred
CTOEIF16Command Time-out Error Interrupt Flag bit
  • 0 Command time-out error has not occurred
  • 1 Command time-out error has occurred
EIF15Error Interrupt Flag bit
  • 0 No error was detected
  • 1 Error was detected
CARDIF8Card Interrupt Status bit
  • 0 Do not generate card interrupt
  • 1 Generate card interrupt
CARDRIF7Card Removal Interrupt Flag bit
  • 0 Card state is stable or debouncing
  • 1 Card has been removed
CARDIIF6Card Insertion Interrupt Flag bit
  • 0 Card state is stable or debouncing
  • 1 Card has been inserted
BRRDYIF5Buffer Read Ready Interrupt Flag bit
  • 0 Not ready to read buffer
  • 1 Ready to read buffer
BWRDYIF4Buffer Write Ready Interrupt Flag bit
  • 0 Not ready to write buffer
  • 1 Ready to write buffer
DMAIF3DMA Interrupt Status bit
  • 0 DMA interrupt was not generated
  • 1 DMA interrupt was generated
BGIF2Block Gap Interrupt Flag bit
  • 0 No block gap event has occurred
  • 1 Transaction stopped at block gap
TXCIF1
CCIF0

SDHCINTENSDHC Interrupt Flag Enable Register

Address
0xBF8EC034
Reset
0x00000000
Access
read/write
Size
32-bit
20 fields
FieldBitsWhat it does
ADEIE25
ACEIE24
CLEIE23
DEBEIE22
DCRCEIE21
DTOEIE20
CIDXEIE19
CEBEIE18
CCRCEIE17
CTOEIE16
EIE15
CARDIE8Card Interrupt Flag Enable bit
  • 0 Card interrupt flag is masked
  • 1 Card interrupt flag is enabled
CARDRIE7Card Removal Interrupt Flag Enable bit
  • 0 Card removal interrupt flag is masked
  • 1 Card removal interrupt flag is enabled
CARDIIE6Card Insertion Interrupt Flag Enable bit
  • 0 Card insertion interrupt flag is masked
  • 1 Card insertion interrupt flag is enabled
BRRDYIE5Buffer Read Ready Interrupt Flag Enable bit
  • 0 Buffer read ready interrupt flag is masked
  • 1 Buffer read ready interrupt flag is enabled
BWRDYIE4Buffer Write Ready Interrupt Flag Enable bit
  • 0 Buffer write ready interrupt flag is masked
  • 1 Buffer write ready interrupt flag is enabled
DMAIE3DMA Interrupt Flag Enable bit
  • 0 DMA interrupt flag is masked
  • 1 DMA interrupt flag is enabled
BGIE2Block Gap Interrupt Flag Enable bit
  • 0 Block gap event interrupt flag is masked
  • 1 Block gap event interrupt flag is enabled
TXCIE1
CCIE0

SDHCINTSENSDHC Interrupt Signal Enable Register

Address
0xBF8EC038
Reset
0x00000000
Access
read/write
Size
32-bit
20 fields
FieldBitsWhat it does
ADEISE25ADMA Error Interrupt Signal Enable bit
  • 0 ADMA error signal is masked
  • 1 ADMA error signal is enabled
ACEISE24Auto CMD12 Error Interrupt Signal Enable bit
  • 0 Auto CMD12 error signal is masked
  • 1 Auto CMD12 error signal is enabled
CLEISE23Current-Limit Error Interrupt Signal Enable bit
  • 0 Current-limit error signal is masked
  • 1 Current-limit error signal is enabled
DEBEISE22Data End Bit Error Interrupt Signal Enable bit
  • 0 Data end bit error signal is masked
  • 1 Data end bit error signal is enabled
DCRCEISE21Data CRC Error Interrupt Signal Enable bit
  • 0 Data CRC error signal is masked
  • 1 Data CRC error signal is enabled
DTOEISE20Data Time-out Error Interrupt Signal Enable bit
  • 0 Data time-out error signal is masked
  • 1 Data time-out error signal is enabled
CIDXEISE19Command Index Error Interrupt Signal Enable bit
  • 0 Command index error signal is masked
  • 1 Command index error signal is enabled
CEBEISE18Command End Bit Error Interrupt Signal Enable bit
  • 0 Command End bit error signal is masked
  • 1 Command End bit error signal is enabled
CCRCEISE17Command CRC Error Interrupt Signal Enable bit
  • 0 Command CRC error signal is masked
  • 1 Command CRC error signal is enabled
CTOEISE16Command Time-out Error Interrupt Signal Enable bit
  • 0 Command time-out error signal is masked
  • 1 Command time-out error signal is enabled
EISE15
CARDISE8Card Interrupt Signal Enable bit
  • 0 Card interrupt signal is masked
  • 1 Card interrupt signal is enabled
CARDRISE7Card Removal Interrupt Signal Enable bit
  • 0 Card removal signal is masked
  • 1 Card removal signal is enabled
CARDIISE6Card Insertion Interrupt Signal Enable bit
  • 0 Card insertion signal is masked
  • 1 Card insertion signal is enabled
BRRDYISE5Buffer Read Ready Interrupt Signal Enable bit
  • 0 Buffer read ready signal is masked
  • 1 Buffer read ready signal is enabled
BWRDYISE4Buffer Write Ready Interrupt Signal Enable bit
  • 0 Buffer write ready signal is masked
  • 1 Buffer write ready signal is enabled
DMAISE3DMA Interrupt Signal Enable bit
  • 0 DMA interrupt signal is masked
  • 1 DMA interrupt signal is enabled
BGISE2Block Gap Interrupt Signal Enable bit
  • 0 Block gap event signal is masked
  • 1 Block gap event signal is enabled
TXCISE1
CCISE0

SDHCSTAT2SDHC Status Register 2

Address
0xBF8EC03C
Reset
0x00000000
Access
read only
Size
32-bit
6 fields
FieldBitsWhat it does
CNISSE7Command Not Issued by Auto CMD12 Error bit
  • 0 No error
  • 1 Command was not issued
ACIDXE4Auto CMD12 Index Error bit
  • 0 Index error was not generated
  • 1 Index error was generated
ACEBE3Auto CMD12 End Bit Error bit
  • 0 End bit error was not generated
  • 1 End bit error was generated
ACCRCE2Auto CMD12 CRC Error bit
  • 0 CRC error was not generated
  • 1 CRC error was generated
ACTOE1Auto CMD12 Time-out Error bit
  • 0 Time-out error was not generated
  • 1 Time-out error was generated
ACNEXEC0Auto CMD12 Not Executed bit
  • 0 Auto CMD12 was executed
  • 1 Auto CMD12 was not executed

SDHCCAPSDHC Capabilities Register

Address
0xBF8EC040
Reset
0x00000000
Access
read only
Size
32-bit
11 fields
FieldBitsWhat it does
VOLT3V3263.3V Voltage Support bit
  • 0 Voltage of 3.3V is supported
SRESUME25Suspend/Resume Support bit
  • 0 Suspend/resume is supported
  • 0 Suspend/resume is not supported
HISPEED23High-speed Support bit
  • 0 High speed is supported
  • 0 High speed is not supported
ADMA221ADMA2 Support bit
  • 0 ADMA2 is supported
  • 0 ADMA2 is not supported
EIGHTBIT20
MBLEN19:18Maximum Block Length bits
  • 0 Reserved
  • 0 2048
  • 0 1024
  • 0 512
BASECLK15:8Base Clock Frequency for SDCLK bits
  • 0 Reserved
  • 1 1 MHz
  • 2 2 MHz
  • 61 61 MHz
  • 62 62 MHz
  • 63 63 MHz
TOCLKU7Time-out Clock Unit bit
  • 0 Time-out clock unit is in MHz
  • 1 Time-out clock unit is in kHz
TOCLKFREQ5:0Time-out Clock Frequency bits
  • 0 Reserved
  • 32 1 kHz or 1 MHz
  • 64 2 kHz or 2 MHz
  • 1952 61 kHz or 61 MHz
  • 1984 62 kHz or 62 MHz
  • 2016 63 kHz or 63 MHz
SLOTTYPE1:0
ASYNCINT31

SDHCMAXCAPSDHC Maximum Current Capabilities Register

Address
0xBF8EC048
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
MC3V37:0Maximum Current for 3.3V bits
  • 0 Reserved
  • 1 4 mA
  • 2 8 mA
  • 3 12 mA
  • 253 1012 mA
  • 254 1016 mA
  • 255 1020 mA

SDHCFESDHC Force Event Register

Address
0xBF8EC050
Reset
0x00000000
Access
write only
Size
32-bit
16 fields
FieldBitsWhat it does
FEAE25
FEACE24Force Event for Auto CMD 12 Error bit
  • 0 Interrupt was not generated
  • 1 Interrupt was generated
FECLE23Force Event for Current-Limit Error bit
  • 0 Interrupt was not generated
  • 1 Interrupt was generated
FEDEBE22Force Event for Data End Bit Error bit
  • 0 Interrupt was not generated
  • 1 Interrupt was generated
FEDCRCE21Force Event for Data CRC Error bit
  • 0 Interrupt was not generated
  • 1 Interrupt was generated
FEDTOE20Force Event for Data Time-out Error bit
  • 0 Interrupt was not generated
  • 1 Interrupt was generated
FEIDXE19Force Event for Command Index Error bit
  • 0 Interrupt was not generated
  • 1 Interrupt was generated
FECEBE18Force Event for Command End Bit Error bit
  • 0 Interrupt was not generated
  • 1 Interrupt was generated
FECCRCE17Force Event for Command CRC Error bit
  • 0 Interrupt was not generated
  • 1 Interrupt was generated
FECTOE16Force Event for Command Time-out Error bit
  • 0 Interrupt was not generated
  • 1 Interrupt was generated
FECNIACE7Force Event for Command Not Issued by Auto CMD12 Error bit
  • 0 Interrupt was not generated
  • 1 Interrupt was generated
FEACIDXERR4
FEACEBERR3
FEACCRCERR2
FEACTOERR1
FEACNEXECERR0

SDHCAESTAT

Address
0xBF8EC054
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
ALMERR2
AERRST1:0

SDHCASADDR

Address
0xBF8EC058
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADDR31:0