WBZ350 ADCHS Registers – 129 with their bits and fields

ADCCON1

Address: 0x44001400
Reset: 0x00000000
Access: read/write
Size: 32-bit

13 fields

Field	Bits	What it does
FRACT	23	Fractional Data Output Format bit `0` Integer `1` Fractional
SELRES	22:21	Shared ADC7 Resolution bits `0` 6 bits `1` 8 bits `2` 10 bits `3` 12 bits (default)
STRGSRC	20:16	Scan Trigger Source Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` RESERVED `4` INT0 `5` ADC_TRIG_5 `6` ADC_TRIG_6 `7` ADC_TRIG_7 `8` ADC_TRIG_8 `9` ADC_TRIG_9 `10` ADC_TRIG_10 `11` ADC_TRIG_11 `12` ADC_TRIG_12 `13` ADC_TRIG_13 `14` ADC_TRIG_14 `15` ADC_TRIG_15 `16` ADC_TRIG_16 `31` External trigger for validation
ON	15	ADC Module Enable bit `0` ADC module is disabled `1` ADC module is enabled
FRZ	14
SIDL	13	Stop in Idle Mode bit `0` Continue module operation in Idle mode `1` Discontinue module operation when device enters Idle mode
CVD_EN	11	CVD Enable bit
FSYDMA	10
FSYUPB	9
SCANEN	8
IRQVS	6:4	Interrupt Vector Shift bits `0` Shift x left 0 bit position `1` Shift x left 1 bit position `2` Shift x left 2 bit position `3` Shift x left 3 bit position `4` Shift x left 4 bit position `5` Shift x left 5 bit position `6` Shift x left 6 bit position `7` Shift x left 7 bit position
STRGLVL	3	Scan Trigger High Level/Positive Edge Sensitivity bit `0` Scan trigger is positive edge sensitive. Once STRIG mode is selected only a single scan trigger will be generated which will complete the scan of all selected analog inputs. (TRGSRCx in the ADCTRGx register) `1` Scan trigger is high level sensitive. Once STRIG mode is selected the scan trigger will continue for all selected analog inputs
DMABL	2:0	DMA to System RAM Buffer Length Size bits `0` Allocates 1 location in system memory to each analog input `1` Allocates 2 locations in system memory to each analog input `2` Allocates 4 locations in system memory to each analog input `3` Allocates 8 locations in system memory to each analog input `4` Allocates 16 locations in system memory to each analog input `5` Allocates 32 locations in system memory to each analog input `6` Allocates 64 locations in system memory to each analog input `7` Allocates 128 locations in system memory to each analog input

ADCCON1CLRBit clear register

Address: 0x44001404
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCON1SETBit set register

Address: 0x44001408
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCON1INVBit invert register

Address: 0x4400140C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCON2

Address: 0x44001410
Reset: 0x00000000
Access: read/write
Size: 32-bit

11 fields

Field	Bits	What it does
REFFLT	30	Band Gap/ Vref / AVdd BOR Fault Status bit `0` Band gap and Vref voltage are working properly `1` Fault in band gap or the Vref voltage while the ON bit (ADCCON1) was set. Most likely a band gap or Vref fault will be caused by a BOR of the analog Vdd supply.
EOSRDY	29	End of Scan Interrupt Status bit `0` Scanning has not completed `1` All analog inputs are considered for scanning through the scan trigger (all analog inputs specified in the ADCCSS1 and ADCCSS2 registers) have completed scanning
CVD_CPL	28:26	CVD Partly Line Capacitor Setting bits
SAMC	25:16	Sample Time for the Shared ADC (ADC7) bits
BGVRIEN	15	Band Gap/ Vref Voltage Ready Interrupt Enable bit `0` No interrupt is generated when the BGVRRDY bit is set `1` Interrupt will be generated when the BGVRDDY bit is set
REFFLTIEN	14	Band Gap/ Vref Voltage Fault Interrupt Enable bit `0` No interrupt is generated when the REFFLT bit is set `1` Interrupt will be generated when the REFFLT bit is set
EOSIEN	13	End of Scan Interrupt Enable bit `0` No interrupt is generated when the EOSRDY bit is set `1` Interrupt will be generated when EOSRDY bit is set
ENXCNVRT	11
ADCEIS	10:8	Shared ADC Early Interrupt Select bits `0` The data ready interrupt is generated 1 ADC module clock prior to end of conversion `1` The data ready interrupt is generated 2 ADC module clocks prior to end of conversion `2` The data ready interrupt is generated 3 ADC clocks prior to end of conversion `3` The data ready interrupt is generated 4 ADC clocks prior to end of conversion `4` The data ready interrupt is generated 5 ADC clocks prior to end of conversion `5` The data ready interrupt is generated 6 ADC clocks prior to end of conversion `6` The data ready interrupt is generated 7 ADC clocks prior to end of conversion `7` The data ready interrupt is generated 8 ADC clocks prior to end of conversion
ADCDIV	6:0	Shared ADC Clock Divider bits
BGVRRDY	31	Band Gap Voltage/ADC Reference Voltage Status bit `0` Either or both band gap voltage and ADC reference voltages (Vref) are not ready `1` Both band gap voltage and ADC reference voltages (Vref) are ready

ADCCON2CLRBit clear register

Address: 0x44001414
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCON2SETBit set register

Address: 0x44001418
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCON2INVBit invert register

Address: 0x4400141C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCON3

Address: 0x44001420
Reset: 0x00000000
Access: read/write
Size: 32-bit

12 fields

Field	Bits	What it does
CONCLKDIV	29:24	Analog-to-Digital Control Clock Divider bits
DIGEN7	23	Shared ADC (ADC7) Digital Enable bit
VREFSEL	15:13	Voltage Reference Input Selection bits `0` ADC VREFH is AVDD, ADC VREFL is AVSS
TRGSUSP	12	Trigger Suspend bit `0` Triggers are not blocked `1` Triggers are blocked from starting a new analog-to-digital conversion
UPDIEN	11	Update Ready Interrupt Enable bit `0` No interrupt is generated `1` Interrupt will be generated when the UPDRDY bit is set by hardware
UPDRDY	10	ADC Update Ready Status bit `0` ADC SFRs cannot be updated `1` ADC SFRs can be updated
SAMP	9	Shared ADC7 Analog Input Sampling Enable bit `0` The ADC S&H amplifier is holding `1` The ADC S&H amplifier is sampling
RQCNVRT	8	Individual ADC Input Conversion Request bit `0` Do not trigger the conversion `1` Trigger the conversion of the selected ADC input as specified by the ADINSEL bits
GLSWTRG	7	Global Level Software Trigger bit `0` Do not trigger an analog-to-digital conversion `1` Trigger conversion for ADC inputs that have selected the GLSWTRG bit as the trigger signal
GSWTRG	6	Global Software Trigger bit `0` Do not trigger an analog-to-digital conversion `1` Trigger conversion for ADC inputs that have selected the GSWTRG bit as either through the associated TRGSRC bits in the ADCTRGx registers or through the STRGSRC<4:0> bits in the ADCCON1 register the trigger signal
ADINSEL	5:0	Analog Input Select bits `0` AN0 `1` AN1 `2` AN2 `3` AN3 `4` AN4 `5` AN5 `6` AN6 `7` AN7 `8` BandGap Reference (internal AN8) `9` IVref 1.2V (internal AN9) `10` VBAT/2 (internal AN10) `11` CTMU Temperature Sensor (internal AN11)
ADCSEL	31:30	Analog-to-Digital Clock Source bits `0` PBCLK1 `1` FRC `2` REFCLK3 `3` SYSCLK

ADCCON3CLRBit clear register

Address: 0x44001424
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCON3SETBit set register

Address: 0x44001428
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCON3INVBit invert register

Address: 0x4400142C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCIMCON1

Address: 0x44001440
Reset: 0x00000000
Access: read/write
Size: 32-bit

24 fields

Field	Bits	What it does
DIFF11	23	AN11 Mode bit `0` AN11 is using Single-ended mode `1` Selects AN11 differential input pair as AN11+ and ANN0-
SIGN11	22	AN11 Signed Data Mode bit `0` AN11 is using Unsigned Data mode `1` AN11 is using Signed Data mode
DIFF10	21	AN10 Mode bit `0` AN10 is using Single-ended mode `1` Selects AN10 differential input pair as AN10+ and ANN0-
SIGN10	20	AN10 Signed Data Mode bit `0` AN10 is using Unsigned Data mode `1` AN10 is using Signed Data mode
DIFF9	19	AN9 Mode bit `0` AN9 is using Single-ended mode `1` Selects AN9 differential input pair as AN9+ and ANN0-
SIGN9	18	AN9 Signed Data Mode bit `0` AN9 is using Unsigned Data mode `1` AN9 is using Signed Data mode
DIFF8	17	AN 8 Mode bit `0` AN8 is using Single-ended mode `1` Selects AN8 differential input pair as AN8+ and ANN0-
SIGN8	16	AN8 Signed Data Mode bit `0` AN8 is using Unsigned Data mode `1` AN8 is using Signed Data mode
DIFF7	15	AN7 Mode bit `0` AN7 is using Single-ended mode `1` Selects AN7 differential input pair as AN7+ and ANN0-
SIGN7	14	AN7 Signed Data Mode bit `0` AN7 is using Unsigned Data mode `1` AN7 is using Signed Data mode
DIFF6	13	AN6 Mode bit `0` AN6 is using Single-ended mode `1` Selects AN6 differential input pair as AN6+ and ANN0-
SIGN6	12	AN6 Signed Data Mode bit `0` AN6 is using Unsigned Data mode `1` AN6 is using Signed Data mode
DIFF5	11	AN5 Mode bit `0` AN5 is using Single-ended mode `1` Selects AN5 differential input pair as AN5+ and ANN0-
SIGN5	10	AN5 Signed Data Mode bit `0` AN5 is using Unsigned Data mode `1` AN5 is using Signed Data mode
DIFF4	9	AN4 Mode bit `0` AN4 is using Single-ended mode `1` Selects AN4 differential input pair as AN4+ and ANN0-
SIGN4	8	AN4 Signed Data Mode bit `0` AN4 is using Unsigned Data mode `1` AN4 is using Signed Data mode
DIFF3	7	AN3 Mode bit `0` AN3 is using Single-ended mode `1` Selects AN3 differential input pair as AN3+ and ANN0-
SIGN3	6	AN3 Signed Data Mode bit `0` AN3 is using Unsigned Data mode `1` AN3 is using Signed Data mode
DIFF2	5	AN2 Mode bit `0` AN2 is using Single-ended mode `1` Selects AN2 differential input pair as AN2+ and ANN0-
SIGN2	4	AN2 Signed Data Mode bit `0` AN2 is using Unsigned Data mode `1` AN2 is using Signed Data mode
DIFF1	3	AN1 Mode bit `0` AN1 is using Single-ended mode `1` Selects AN1 differential input pair as AN1+ and ANN0-
SIGN1	2	AN1 Signed Data Mode bit `0` AN1 is using Unsigned Data mode `1` AN1 is using Signed Data mode
DIFF0	1	AN0 Mode bit `0` AN0 is using Single-ended mode `1` Selects AN0 differential input pair as AN0+ and ANN0-
SIGN0	0	AN0 Signed Data Mode bit `0` AN0 is using Unsigned Data mode `1` AN0 is using Signed Data mode

ADCIMOD1CLRBit clear register

Address: 0x44001444
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCIMOD1SETBit set register

Address: 0x44001448
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCIMOD1INVBit invert register

Address: 0x4400144C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCGIRQEN1

Address: 0x44001480
Reset: 0x00000000
Access: read/write
Size: 32-bit

12 fields

Field	Bits	What it does
AGIEN11	11	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN10	10	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN9	9	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN8	8	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN7	7	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN6	6	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN5	5	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN4	4	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN3	3	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN2	2	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN1	1	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN0	0	ADC Global Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)

ADCGIRQEN1CLRBit clear register

Address: 0x44001484
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCGIRQEN1SETBit set register

Address: 0x44001488
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCGIRQEN1INVBit invert register

Address: 0x4400148C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCSS1

Address: 0x440014A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

12 fields

Field	Bits	What it does
CSS11	11	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS10	10	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS9	9	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS8	8	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS7	7	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS6	6	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS5	5	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS4	4	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS3	3	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS2	2	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS1	1	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS0	0	Analog Common Scan Select bits `0` Skip ANx for input scan `1` Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)

ADCCSS1CLRBit clear register

Address: 0x440014A4
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCSS1SETBit set register

Address: 0x440014A8
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCSS1INVBit invert register

Address: 0x440014AC
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCDSTAT1

Address: 0x440014C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

12 fields

Field	Bits	What it does
ARDY11	11
ARDY10	10
ARDY9	9
ARDY8	8
ARDY7	7
ARDY6	6
ARDY5	5
ARDY4	4
ARDY3	3
ARDY2	2
ARDY1	1
ARDY0	0

ADCDSTAT1CLRBit clear register

Address: 0x440014C4
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCDSTAT1SETBit set register

Address: 0x440014C8
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCDSTAT1INVBit invert register

Address: 0x440014CC
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCMPEN1

Address: 0x440014E0
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
CMPE7	7
CMPE6	6
CMPE5	5
CMPE4	4
CMPE3	3
CMPE2	2
CMPE1	1
CMPE0	0

ADCCMPEN0CLRBit clear register

Address: 0x440014E4
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCMPEN0SETBit set register

Address: 0x440014E8
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCMPEN0INVBit invert register

Address: 0x440014EC
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCMP1

Address: 0x440014F0
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
ADCMPLO	15:0
ADCMPHI	31:16

ADCCMP0CLRBit clear register

Address: 0x440014F4
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCMP0SETBit set register

Address: 0x440014F8
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCMP0INVBit invert register

Address: 0x440014FC
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCMPEN2

Address: 0x44001500
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
CMPE7	7
CMPE6	6
CMPE5	5
CMPE4	4
CMPE3	3
CMPE2	2
CMPE1	1
CMPE0	0

ADCCMPEN1CLRBit clear register

Address: 0x44001504
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCMPEN1SETBit set register

Address: 0x44001508
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCMPEN1INVBit invert register

Address: 0x4400150C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCMP2

Address: 0x44001510
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
ADCMPLO	15:0
ADCMPHI	31:16

ADDCMP1CLRBit clear register

Address: 0x44001514
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADDCMP1SETBit set register

Address: 0x44001518
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADDCMP1INVBit invert register

Address: 0x4400151C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCFLTR1

Address: 0x440015A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
DATA16EN0	30
ADFMODE0	29
OVRSAM0	28:26
AFIEN0	25
AFIF0	24
FLTINID0	20:16
FLT_DATA0	15:0
AFEN0	31

ADCFLTR0CLRBit clear register

Address: 0x440015A4
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCFLTR0SETBit set register

Address: 0x440015A8
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCFLTR0INVBit invert register

Address: 0x440015AC
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCFLTR2

Address: 0x440015B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
DATA16EN1	30
ADFMODE1	29
OVRSAM1	28:26
AFIEN1	25
AFIF1	24
FLTINID1	20:16
FLT_DATA1	15:0
AFEN1	31

ADCFLTR1CLRBit clear register

Address: 0x440015B4
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCFLTR1SETBit set register

Address: 0x440015B8
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCFLTR1INVBit invert register

Address: 0x440015BC
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCTRG1ADC Trigger Source 1 Register

Address: 0x44001600
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TRGSRC3	28:24	Trigger Source for Conversion of ADC3 Module Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger `4` INT0 `5` ADC_TRIG_5 `6` ADC_TRIG_6 `7` ADC_TRIG_7 `8` ADC_TRIG_8 `9` ADC_TRIG_9 `10` ADC_TRIG_10 `11` ADC_TRIG_11 `12` ADC_TRIG_12 `13` ADC_TRIG_13 `14` ADC_TRIG_14 `15` ADC_TRIG_15 `16` ADC_TRIG_16 `31` RESERVED
TRGSRC2	20:16	Trigger Source for Conversion of ADC2 Module Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger `4` INT0 `5` ADC_TRIG_5 `6` ADC_TRIG_6 `7` ADC_TRIG_7 `8` ADC_TRIG_8 `9` ADC_TRIG_9 `10` ADC_TRIG_10 `11` ADC_TRIG_11 `12` ADC_TRIG_12 `13` ADC_TRIG_13 `14` ADC_TRIG_14 `15` ADC_TRIG_15 `16` ADC_TRIG_16 `31` RESERVED
TRGSRC1	12:8	Trigger Source for Conversion of ADC1 Module Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger `4` INT0 `5` ADC_TRIG_5 `6` ADC_TRIG_6 `7` ADC_TRIG_7 `8` ADC_TRIG_8 `9` ADC_TRIG_9 `10` ADC_TRIG_10 `11` ADC_TRIG_11 `12` ADC_TRIG_12 `13` ADC_TRIG_13 `14` ADC_TRIG_14 `15` ADC_TRIG_15 `16` ADC_TRIG_16 `31` RESERVED
TRGSRC0	4:0	Trigger Source for Conversion of ADC0 Module Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger `4` INT0 `5` ADC_TRIG_5 `6` ADC_TRIG_6 `7` ADC_TRIG_7 `8` ADC_TRIG_8 `9` ADC_TRIG_9 `10` ADC_TRIG_10 `11` ADC_TRIG_11 `12` ADC_TRIG_12 `13` ADC_TRIG_13 `14` ADC_TRIG_14 `15` ADC_TRIG_15 `16` ADC_TRIG_16 `31` RESERVED

ADCTRG1CLRBit clear register

Address: 0x44001604
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCTRG1SETBit set register

Address: 0x44001608
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCTRG1INVBit invert register

Address: 0x4400160C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCTRG2ADC Trigger Source 2 Register

Address: 0x44001610
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TRGSRC7	28:24	Trigger Source for Conversion of ADC7 Module Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger `4` INT0 `5` ADC_TRIG_5 `6` ADC_TRIG_6 `7` ADC_TRIG_7 `8` ADC_TRIG_8 `9` ADC_TRIG_9 `10` ADC_TRIG_10 `11` ADC_TRIG_11 `12` ADC_TRIG_12 `13` ADC_TRIG_13 `14` ADC_TRIG_14 `15` ADC_TRIG_15 `16` ADC_TRIG_16 `31` RESERVED
TRGSRC6	20:16	Trigger Source for Conversion of ADC6 Module Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger `4` INT0 `5` ADC_TRIG_5 `6` ADC_TRIG_6 `7` ADC_TRIG_7 `8` ADC_TRIG_8 `9` ADC_TRIG_9 `10` ADC_TRIG_10 `11` ADC_TRIG_11 `12` ADC_TRIG_12 `13` ADC_TRIG_13 `14` ADC_TRIG_14 `15` ADC_TRIG_15 `16` ADC_TRIG_16 `31` RESERVED
TRGSRC5	12:8	Trigger Source for Conversion of ADC5 Module Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger `4` INT0 `5` ADC_TRIG_5 `6` ADC_TRIG_6 `7` ADC_TRIG_7 `8` ADC_TRIG_8 `9` ADC_TRIG_9 `10` ADC_TRIG_10 `11` ADC_TRIG_11 `12` ADC_TRIG_12 `13` ADC_TRIG_13 `14` ADC_TRIG_14 `15` ADC_TRIG_15 `16` ADC_TRIG_16 `31` RESERVED
TRGSRC4	4:0	Trigger Source for Conversion of ADC4 Module Select bits `0` No Trigger `1` Software edge trigger `2` Software level trigger `3` Scan trigger `4` INT0 `5` ADC_TRIG_5 `6` ADC_TRIG_6 `7` ADC_TRIG_7 `8` ADC_TRIG_8 `9` ADC_TRIG_9 `10` ADC_TRIG_10 `11` ADC_TRIG_11 `12` ADC_TRIG_12 `13` ADC_TRIG_13 `14` ADC_TRIG_14 `15` ADC_TRIG_15 `16` ADC_TRIG_16 `31` RESERVED

ADTRG2CLRBit clear register

Address: 0x44001614
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADTRG2SETBit set register

Address: 0x44001618
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADTRG2INVBit invert register

Address: 0x4400161C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADTRG3CLRBit clear register

Address: 0x44001624
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADTRG3SETBit set register

Address: 0x44001628
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADTRG3INVBit invert register

Address: 0x4400162C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCMPCON1

Address: 0x44001680
Reset: 0x00000000
Access: read/write
Size: 32-bit

10 fields

Field	Bits	What it does
CMPINID0	13:8
ENDCMP	7
DCMPIEN	6
DCMPED	5
IEBTWN	4
IEHIHI	3
IEHILO	2
IELOHI	1
IELOLO	0
CVD_DATA	31:16

ADCCMPCON1CLRBit clear register

Address: 0x44001684
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCMPCON1SETBit set register

Address: 0x44001688
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCMPCON1INVBit invert register

Address: 0x4400168C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCMPCON2

Address: 0x44001690
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
AINID	12:8
ENDCMP	7
DCMPGIEN	6
DCMPED	5
IEBTWN	4
IEHIHI	3
IEHILO	2
IELOHI	1
IELOLO	0

ADCMPCON2CLRBit clear register

Address: 0x44001694
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCMPCON2SETBit set register

Address: 0x44001698
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCMPCON2INVBit invert register

Address: 0x4400169C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCFSTATCLRBit clear register

Address: 0x440016E4
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCFSTATSETBit set register

Address: 0x440016E8
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCFSTATINVBit invert register

Address: 0x440016EC
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCFIFOCLRBit clear register

Address: 0x440016F4
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCFIFOSETBit set register

Address: 0x440016F8
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCFIFOINVBit invert register

Address: 0x440016FC
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCBASE

Address: 0x44001700
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ADCBASE	15:0

ADCBASECLRBit clear register

Address: 0x44001704
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCBASESETBit set register

Address: 0x44001708
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCBASEINVBit invert register

Address: 0x4400170C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCDMASTATCLRBit clear register

Address: 0x44001714
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCDMASTATSETBit set register

Address: 0x44001718
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCDMASTATINVBit invert register

Address: 0x4400171C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCNTB

Address: 0x44001720
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ADCCNTB	31:0

ADCCNTBCLRBit clear register

Address: 0x44001724
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCNTBSETBit set register

Address: 0x44001728
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCCNTBINVBit invert register

Address: 0x4400172C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCDMAB

Address: 0x44001730
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ADDMAB	31:0

ADCDMABCLRBit clear register

Address: 0x44001734
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCDMABSETBit set register

Address: 0x44001738
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCDMABINVBit invert register

Address: 0x4400173C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCTRGSNS

Address: 0x44001740
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
LVL7	7
LVL6	6
LVL5	5
LVL4	4
LVL3	3
LVL2	2
LVL1	1
LVL0	0

ADCTRGSNSCLRBit clear register

Address: 0x44001744
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCTRGSNSSETBit set register

Address: 0x44001748
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCTRGSNSINVBit invert register

Address: 0x4400174C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADC0TIMECLRBit clear register

Address: 0x44001754
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADC0TIMESETBit set register

Address: 0x44001758
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADC0TIMEINVBit invert register

Address: 0x4400175C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCEISTAT1CLRBit clear register

Address: 0x440017E4
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCEISTAT1SETBit set register

Address: 0x440017E8
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCEISTAT1INVBit invert register

Address: 0x440017EC
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCANCON

Address: 0x44001800
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
WKUPCLKCNT	27:24
WKIEN7	23
WKRDY7	15
ANEN7	7

ADCANLCTLCLRBit clear register

Address: 0x44001804
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCANLCTLSETBit set register

Address: 0x44001808
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCANLCTLINVBit invert register

Address: 0x4400180C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADC7CFG

Address: 0x44001A70
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ADC7CFG	31:0

ADCFGSHRCLRBit clear register

Address: 0x44001A74
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCFGSHRSETBit set register

Address: 0x44001A78
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCFGSHRINVBit invert register

Address: 0x44001A7C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCSVCONCLRBit clear register

Address: 0x44001A84
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCSVCONSETBit set register

Address: 0x44001A88
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCSVCONINVBit invert register

Address: 0x44001A8C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCSYSCFG0

Address: 0x44001B00
Reset: 0x00000000
Access: read/write
Size: 32-bit

12 fields

Field	Bits	What it does
AN11	11
AN10	10
AN9	9
AN8	8
AN7	7
AN6	6
AN5	5
AN4	4
AN3	3
AN2	2
AN1	1
AN0	0

ADCSYSCFG0CLRBit clear register

Address: 0x44001B04
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCSYSCFG0SETBit set register

Address: 0x44001B08
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCSYSCFG0INVBit invert register

Address: 0x44001B0C
Reset: 0x00000000
Access: read/write
Size: 32-bit

ADCDATA0

Address: 0x44001E00
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA1

Address: 0x44001E10
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA2

Address: 0x44001E20
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA3

Address: 0x44001E30
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA4

Address: 0x44001E40
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA5

Address: 0x44001E50
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA6

Address: 0x44001E60
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA7

Address: 0x44001E70
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA8

Address: 0x44001E80
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA9

Address: 0x44001E90
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA10

Address: 0x44001EA0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCDATA11

Address: 0x44001EB0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DATA	31:0

ADCHS 12-bit Analog to Digital Converter

ADCHS 12-bit Analog to Digital Converter