WBZ350 CFG registers
The 56 registers of CFG, from 0x44000000, with their reset value and every field. The WBZ350 has 2134 registers in 59 peripherals, one page each.
CFG
CFGCON0
- Address
0x44000000- Reset
0x7100000B- Access
- read/write
- Size
- 32-bit
23 fields
| Field | Bits | What it does |
|---|
| FRECCDIS | 30 | Flex RAM ECC Control |
| FECCCON | 29:28 | Flash ECC Control |
| INT0P | 26 | INT0P Polarity |
| INT0E | 25 | INT0 Enable |
| PCM | 24 | PCHE I/D Cacheable Mode |
| SLRTEN1 | 22 | SLRT Enable for SERCOM1 |
| SLRTEN0 | 21 | SLRT Enable for SERCOM0 |
| HPLUGDIS | 20 | Hot Plugging Disable |
| SMBUSEN1 | 18 | SMBus Enable for SERCOM1 |
| SMBUSEN0 | 17 | SMBus Enable for SERCOM0 |
| CFGCLOCK | 15:14 | Configuration Register Lock |
| IOLOCK | 13 | IO LOCK |
| PMDLOCK | 12 | Peripheral Module Disable (PMD) LOCK |
| PGLCOK | 11 | Permission Group LOCK |
| PMULOCK | 10 | PMU Controller Register LOCK |
| RTCOUT_ALTEN | 9 | RTCOUT Alternate Enable |
| RTCIN0_ALTEN | 8 | RTCIN0 Alternate Enable |
| CPENFILT | 7 | ADC CP Filter Enable |
| ACCMP1_ALTEN | 6 | AC CMP1 Alternate Enable |
| ADCPOVR | 4 | ADC Charge Pump Override |
| JTAGEN | 3 | JTAG Enable |
| TROEN | 2 | Trace Output Enable |
| SWOEN | 1 | SWO enable on 2-wire debug interface |
CFGCON0CLRBit clear register
- Address
0x44000004- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGCON0SETBit set register
- Address
0x44000008- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGCON0INVBit invert register
- Address
0x4400000C- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGCON1
- Address
0x44000010- Reset
0x1F00403B- Access
- read/write
- Size
- 32-bit
18 fields
| Field | Bits | What it does |
|---|
| CLKZBREF | 30 | External Reference Clock ZB Enable |
| QSPIDDRM | 29 | QSPI DDR Mode Clock Enable |
| WDTPSS | 28:24 | Watchdog Timer Post-scale Select Sleep |
| I2CDSEL1 | 22 | I2C Delay Select for SERCOM1 |
| I2CDSEL0 | 21 | I2C Delay Select for SERCOM0 |
| CCL_OE | 20 | CCL Pads (via PPS) Output Enable |
| SCOM1_HSEN | 18 | SERCOM1 (Direct)High Speed Pin Enable |
| SCOM0_HSEN | 17 | SERCOM0 (Direct)High Speed Pin Enable |
| QSPI_HSEN | 16 | QSPI (Direct) Enable |
| QSCHE_EN | 15 | QSPI Address Space Cache Attribute |
| SMCLR | 14 | Selects CRU handling of MCLR Control |
| SLRCTRL1 | 12 | I2C Slew Rate Control for SERCOM1 |
| SLRCTRL0 | 11 | I2C Slew Rate Control for SERCOM0 |
| CMP1_OE | 9 | Analog Comparator-1 Output Enable |
| CMP0_OE | 8 | Analog Comparator-0 Output Enable |
| ZBTWKSYS | 7 | ZBT Subsystem External Wake-up source |
| ECC_SEL_MEM | 6 | ECC row selection bit |
| TRCEN | 5 | Trace Enable |
CFGCON1CLRBit clear register
- Address
0x44000014- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGCON1SETBit set register
- Address
0x44000018- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGCON1INVBit invert register
- Address
0x4400001C- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGCON2
- Address
0x44000020- Reset
0x7F7FFF38- Access
- read/write
- Size
- 32-bit
16 fields
| Field | Bits | What it does |
|---|
| DMTCNT | 30:26 | Dead Man Timer Count Select |
| WDTWINSZ | 25:24 | Watchdog Timer Window Size |
| WDTEN | 23 | Watchdog Timer Enable |
| WINDIS | 22 | Windowed Watchdog Timer Disable |
| WDTSPGM | 21 | Watchdog Timer Stop during Flash Programming |
| WDTPSR | 20:16 | Watchdog Timer Post-scale Select Run |
| FSCMEN | 15 | Fail-Safe Clock Monitor Enable |
| CKSWEN | 14 | Software Clock Switching Enable |
| WAKE2SPD | 13 | 2-Speed startup enabled in Sleep mode |
| SOSCSEL | 12 | SOSC Selection Configuration |
| WDTRMCS | 11:10 | WDT RUN Mode Clock Select |
| POSCMOD | 9:8 | Primary Oscillator Configuration |
| PMUTEST_VDD_EN | 7 | PMU Test Output or VDD/2 Enable via ADC IE12 |
| DMTINTV | 5:3 | Dead Man Timer Count Window Interval |
| ACMP_CYCLE | 2:0 | AC SIB Comparator Result Wait Cycles |
| DMTEN | 31 | Dead Man Timer Enable |
CFGCON2CLRBit clear register
- Address
0x44000024- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGCON2SETBit set register
- Address
0x44000028- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGCON2INVBit invert register
- Address
0x4400002C- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGCON4
- Address
0x44000040- Reset
0x840E4000- Access
- read/write
- Size
- 32-bit
17 fields
| Field | Bits | What it does |
|---|
| LPOSCEN | 30 | Low Power (Secondary) Oscillator Enable |
| UVREGROVR | 29 | ULPVREG Retention Mode Override |
| DSEN | 28 | Deep Sleep Bit Enable |
| DSWDTEN | 27 | Deep Sleep Watchdog Timer Enable |
| DSWDTOSC | 26 | Deep Sleep Watchdog Timer Reference Clock Select |
| DSWDTPS | 25:21 | Deep Sleep Watchdog Timer Postscale Select |
| DSZPBOREN | 20 | Deep Sleep Zero-Power BOR Enable |
| CPEN_DLY | 19:17 | Charge-pump ready digital delay |
| RTCEVTYPE | 16 | RTC Event Type |
| LPCLK_MOD | 15 | LPCLK modifier in counter/delay mode |
| VBKP_DIVSEL | 14 | VDDBUKPCORE LPCLK Clock Divider Selection |
| VBKP_32KCSEL | 13:12 | VDDBUKPCORE 32KHz clock source selection |
| VBKP_1KCSEL | 11 | VDDBUKPCORE LPCLK Clock Selection |
| RTCEVENT_EN | 10 | Pad Output Enable for MCHP legacy RTC event output |
| RTCEVENT_SEL | 9:8 | RTC Event Selection |
| SOSC_CFG | 7:0 | SOSC Configuration |
| RTCNTM_CSEL | 31 | RTC Counter Mode Clock Select |
CFGCON4CLRBit clear register
- Address
0x44000044- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGCON4SETBit set register
- Address
0x44000048- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGCON4INVBit invert register
- Address
0x4400004C- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGPGQOS
- Address
0x44000050- Reset
0xE044004C- Access
- read/write
- Size
- 32-bit
10 fields
| Field | Bits | What it does |
|---|
| FCQOS | 29:28 | FC Controller QOS Control |
| DSUPG | 25:24 | DSU Permission Group |
| CRYPTOQOS | 23:22 | Crypto QOS Control |
| CRYPTOPG | 21:20 | Crypto Permission Group |
| DGISPIQOS | 19:18 | ADC Controller QOS Control |
| DGISPIPG | 17:16 | ADC Controller Permission Group |
| DMAPG | 9:8 | DMA (Rd/Wr) Permission Group |
| CPUQOS | 3:2 | CPU I/D and System Bus QOS Control |
| CPUPG | 1:0 | CPU (Code) Permission Group |
| WISIBQOS | 31:30 | Wireless SIB QOS Control |
CFGPGQOSCLRBit clear register
- Address
0x44000054- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGPGQOSSETBit set register
- Address
0x44000058- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGPGQOSINVBit invert register
- Address
0x4400005C- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGPCLKGEN1
- Address
0x44000060- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
12 fields
| Field | Bits | What it does |
|---|
| CM4TCSEL | 30:28 | CM4T Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| TCC12CD | 23 | TCC1/2 Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| TCC12CSEL | 22:20 | TCC1/2 Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| SERCOM01CD | 15 | SERCOM0/1 Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| SERCOM01CSEL | 14:12 | SERCOM0/1 Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| FREQMMCD | 11 | FREQMMC Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| FREQMMCSEL | 10:8 | FREQMMC Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| FREQMRCD | 7 | FREQMRC Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| FREQMRCSEL | 6:4 | FREQMRC Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| EICCD | 3 | EIC Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| EICCSEL | 2:0 | EIC Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| CM4TCD | 31 | CM4T Clock Disable0 Disable PGCLK1 Enable PGCLK
|
CFGPCLKGEN1CLRBit clear register
- Address
0x44000064- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGPCLKGEN1SETBit set register
- Address
0x44000068- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGPCLKGEN1INVBit invert register
- Address
0x4400006C- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGPCLKGEN2
- Address
0x44000070- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
16 fields
| Field | Bits | What it does |
|---|
| EVSYSC8SEL | 30:28 | EVSYSC8 Peripheral Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| EVSYSC7CD | 27 | EVSYSC7 Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| EVSYSC7SEL | 26:24 | EVSYSC7 Peripheral Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| EVSYSC6CD | 23 | EVSYSC6 Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| EVSYSC6SEL | 22:20 | EVSYSC6 Peripheral Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| EVSYSC5CD | 19 | EVSYSC5 Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| EVSYSC5SEL | 18:16 | EVSYSC5 Peripheral Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| EVSYSC4CD | 15 | EVSYSC4 Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| EVSYSC4SEL | 14:12 | EVSYSC4 Peripheral Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| EVSYSC3CD | 11 | EVSYSC3 Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| EVSYSC3SEL | 10:8 | EVSYSC3 Peripheral Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| EVSYSC2CD | 7 | EVSYSC2 Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| EVSYSC2SEL | 6:4 | EVSYSC2 Peripheral Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| EVSYSC1CD | 3 | EVSYSC1 Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| EVSYSC1SEL | 2:0 | EVSYSC1 Peripheral Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| EVSYSC8CD | 31 | EVSYSC8 Clock Disable0 Disable PGCLK1 Enable PGCLK
|
CFGPCLKGEN2CLRBit clear register
- Address
0x44000074- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGPCLKGEN2SETBit set register
- Address
0x44000078- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGPCLKGEN2INVBit invert register
- Address
0x4400007C- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGPCLKGEN3
- Address
0x44000080- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
12 fields
| Field | Bits | What it does |
|---|
| TCC0CD | 23 | TCC0 Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| TCC0CSEL | 22:20 | TCC0 Peripheral Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| ACCD | 19 | AC Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| ACCSEL | 18:16 | AC Peripheral Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| EVSYSC12CD | 15 | EVSYSC12 Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| EVSYSC12SEL | 14:12 | EVSYSC12 Peripheral Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| EVSYSC11CD | 11 | EVSYSC11 Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| EVSYSC11SEL | 10:8 | EVSYSC11 Peripheral Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| EVSYSC10CD | 7 | EVSYSC10 Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| EVSYSC10SEL | 6:4 | EVSYSC10 Peripheral Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| EVSYSC9CD | 3 | EVSYSC9 Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| EVSYSC9SEL | 2:0 | EVSYSC9 Peripheral Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
CFGPCLKGEN3CLRBit clear register
- Address
0x44000084- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGPCLKGEN3SETBit set register
- Address
0x44000088- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGPCLKGEN3INVBit invert register
- Address
0x4400008C- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGPCLKGEN4
- Address
0x44000090- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
10 fields
| Field | Bits | What it does |
|---|
| TC67CD | 19 | TC67CD Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| TC67CSEL | 18:16 | TC67CSEL Peripheral Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| TC54CD | 15 | TC54CD Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| TC54CSEL | 14:12 | TC54CSEL Peripheral Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| TC23CD | 11 | TC23CD Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| TC23CSEL | 10:8 | TC23CSEL Peripheral Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| TC1CD | 7 | TC1 Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| TC1CSEL | 6:4 | TC1 Peripheral Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
| TC0CD | 3 | TC0 Clock Disable0 Disable PGCLK1 Enable PGCLK
|
| TC0CSEL | 2:0 | TC0 Peripheral Clock Selection0 No Clock1 Reference Clock 12 Reference Clock 23 Reference Clock 34 Reference Clock 45 Reference Clock 56 Reference Clock 67 32 KHz Low Power Clock
|
CFGPCLKGEN4CLRBit clear register
- Address
0x44000094- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGPCLKGEN4SETBit set register
- Address
0x44000098- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
CFGPCLKGEN4INVBit invert register
- Address
0x4400009C- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
USER_ID
- Address
0x440000A0- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
1 field
| Field | Bits | What it does |
|---|
| USER_ID | 15:0 | User unique ID, readable using the SWD USER_ID instruction |
USER_IDCLRBit clear register
- Address
0x440000A4- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
USER_IDSETBit set register
- Address
0x440000A8- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
USER_IDINVBit invert register
- Address
0x440000AC- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
SYSKEY
- Address
0x440000B0- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
1 field
| Field | Bits | What it does |
|---|
| SYSKEY | 31:0 | System Key |
PMD1
- Address
0x440000C0- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
12 fields
| Field | Bits | What it does |
|---|
| QSPIMD | 29 | SQI Module Disable |
| DGISPIMD | 23 | DGI SPI Module Disable |
| RTCCMD | 16 | RTCC Module Disable |
| CVDMD | 9 | Shared ADC SAR Core Module Disable |
| ADCSARMD | 8 | Shared ADC SAR Core Module Disable |
| ADCMD | 7 | ADC Controller Module Disable |
| ACMD | 6 | AC Module Disable |
| PLVDMD | 4 | PLVD Module Disable |
| LPAMD | 3 | RF LPA Module Disable |
| MPAMD | 2 | RF MPA Module Disable |
| BTMD | 1 | Bluetooth Module Disable |
| ZBMD | 0 | ZigBee Module Disable |
PMD1CLRBit clear register
- Address
0x440000C4- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
PMD1SETBit set register
- Address
0x440000C8- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
PMD1INVBit invert register
- Address
0x440000CC- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
PMD2
- Address
0x440000D0- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
6 fields
| Field | Bits | What it does |
|---|
| REFO3MD | 30 | Reference (Clock) Out 3 Module Disable |
| REFO2MD | 29 | Reference (Clock) Out 2 Module Disable |
| REFO1MD | 28 | Reference (Clock) Out 1 Module Disable |
| REFO6MD | 25 | Reference (Clock) Out 6 Module Disable |
| REFO5MD | 24 | Reference (Clock) Out 5 Module Disable |
| REFO4MD | 31 | Reference (Clock) Out 4 Module Disable |
PMD2CLRBit clear register
- Address
0x440000D4- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
PMD2SETBit set register
- Address
0x440000D8- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
PMD2INVBit invert register
- Address
0x440000DC- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
PMD3
- Address
0x440000E0- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
14 fields
| Field | Bits | What it does |
|---|
| TCC2MD | 14 | TCC2 Module Disable |
| TCC1MD | 13 | TCC1 Module Disable |
| TCC0MD | 12 | TCC0 Module Disable |
| TC7MD | 11 | TC7 Module Disable |
| TC6MD | 10 | TC6 Module Disable |
| TC5MD | 9 | TC5 Module Disable |
| TC4MD | 8 | TC4 Module Disable |
| TC3MD | 7 | TC3 Module Disable |
| TC2MD | 6 | TC2 Module Disable |
| TC1MD | 5 | TC1 Module Disable |
| TC0MD | 4 | TC0 Module Disable |
| DACMD | 3 | DAC Module Disable |
| SER1MD | 1 | SERCOM1 Module Disable |
| SER0MD | 0 | SERCOM0 Module Disable |
PMD3CLRBit clear register
- Address
0x440000E4- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
PMD3SETBit set register
- Address
0x440000E8- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
PMD3INVBit invert register
- Address
0x440000EC- Reset
0x00000000- Access
- read/write
- Size
- 32-bit
MISCSTAT
- Address
0x44000100- Reset
0x01000081- Access
- read/write
- Size
- 32-bit
2 fields
| Field | Bits | What it does |
|---|
| CM4SWRST_EN | 11 | CM4 SW Reset Enable |
| CLDORDY | 9 | CLDO Ready |
IDDevice ID
- Address
0x44000140- Reset
0x00000000- Access
- read only
- Size
- 32-bit
BCFG0
- Address
0x44000200- Reset
0x00000000- Access
- read only
- Size
- 32-bit
4 fields
| Field | Bits | What it does |
|---|
| SIGN | 29 | Flash SIGN |
| CP | 28 | Boot Code Protect |
| PCSCMODE | 1 | PCHE Single cache Mode |
| BINFOVALID0 | 31 | First 256-bit BCFG information Valid |
BETA