The 6 registers of DGI_SPI (SPI DMA for DGI Macro), from 0x44003E00, with their reset value and every field. The WBZ350 has 2134 registers in 59 peripherals, one page each.
DGI_SPI SPI DMA for DGI Macro
SPICONSPI control register
Address
0x44003E00
Reset
0x00000000
Access
read/write
Size
32-bit
13 fields
Field
Bits
What it does
MSSEN
28
Master Mode Slave Select Enable bit
0 Slave select SPI support disabled
1 SPI Slave Select support enabled
MCLKEN
23
Master Clock Enable
0 PBCLK is used by the BRG
1 MCLK is used by the BRG
ENHBUF
16
Enhanced Buffer Enable bit
0 Enhanced Buffer Mode is disabled
1 Enhanced Buffer Mode is enabled
ON
15
DGISPI On bit
0 Turn off and reset macro, disable clocks, disable interrupt event generation, allow SFR modifications.
1 Enable macro
FRZ
14
Freeze bit (in Debug Mode)
0 Continue macro operation when in Debug mode
1 Break macro operation when in Debug mode
SIDL
13
Stop in Idle control bit
0 Continue to operate in CPU Idle mode
1 Halt in CPU Idle mode
DISSDO
12
Disable SDO bit
0 SDO pin is controlled by the macro
1 SDO pin is not used by the macro. Pin controlled by PORT function
MODE
11:10
Serial Word Length bits
CKE
8
SPI Clock Edge Select bit
0 Transmit happens on transition from idle clock state to active clock stat e
1 Transmit happens on transition from active clock state to idle clock state
SSCON
7
SSControl bits
0 SS is not controlled by the DMA module
1 SS is asserted for the duration of TXCNT
CKP
6
Clock Polarity Select bit
0 Idle state for clock is a low level; active state is a high level
1 Idle state for clock is a high level; active state is a low level
STXISEL
3:2
SPI Transmit Service Request Interrupt SelectFor enhanced buffer mode, the SPI generates a Transmit Service Request when:
0 The SPIxTXB is empty and SPIxSR is empty (i.e. all transmit operations are complete)
1 The SPIxTXB is empty
2 The SPIxTXB is at least half empty
3 The SPIxTXB is not full
GO
0
DMA Operation Status bitThis bit is set by the user software to start the DMA operation. It is reset back to zero by the DMA engine whenthe DMA operation is completed or aborted by clearing the ON bit.
0 DMA is not in operation
1 DMA is in operation
SPISTATSPI Status register
Address
0x44003E10
Reset
0x00000008
Access
read only
Size
32-bit
5 fields
Field
Bits
What it does
TXBUFELM
20:16
TransmitBuffer Element Count bits (valid only when ENHBUF = 1)
SPIBUSY
11
SPI activity status bit
0 No on-going transactions (at time of read)
1 Macro currently busy with some transactions
SRMT
7
Shift Register (SPIxSR) Empty bit0= There are current or pending transactions
1 There are no current or pending transactions
SPITBE
3
SPI Transmit Buffer Empty status bit
0 SPIxTXB is not empty
1 SPIxTXB is empty
SPITBF
1
SPI Transmit Buffer Full Status bit
0 SPIxTXB not full
1 SPIxTXB is full
SPIBUFSPI BUFFER register
Address
0x44003E20
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATA
31:0
FIFO Data bits
SPIBRGSPI Baud rate register
Address
0x44003E30
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
BRG
12:0
Baud Rate Divisor bitsseeSection 2.4.1.
SPITXADDSPI DMA Transmit Address register
Address
0x44003E40
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXADD
15:0
Transmit Source Address bitsTXADD can constantly be updated to reflect the current transmit address as the transfer progresses
SPITXCNTSPI DMA Transmit Count register
Address
0x44003E50
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXCNT
15:0
Transmit Count bitsThis register indicates the number of transferred data words. As the DMA progresses, TXCNT is constantly decremented to reflect the remaining count yet to be transferred.
BETA