WBZ350 FUSES registers

The 24 registers of FUSES (Non-Volatile Fuses), from 0x00805E80, with their reset value and every field. The WBZ350 has 2134 registers in 59 peripherals, one page each.

FUSES Non-Volatile Fuses

ALTFBCFG7RESERVED

Address
0x00805E80
Reset
0xFFFFFFFF
Access
read/write
Size
32-bit

ALTFBCFG6RESERVED

Address
0x00805E84
Reset
0xFFFFFFFF
Access
read/write
Size
32-bit

ALTFUSERIDALT USERID

Address
0x00805E88
Reset
0x0000FFFF
Access
read/write
Size
32-bit

ALTDEVCFG4ALT CFGCON4 Fuses

Address
0x00805E8C
Reset
0x840E4000
Access
read/write
Size
32-bit

ALTDEVCFG2ALT CFGCON2 Fuses

Address
0x00805E90
Reset
0x5F74FF38
Access
read/write
Size
32-bit

ALTDEVCFG1ALT CFGCON1 Fuses

Address
0x00805E94
Reset
0x1410443B
Access
read/write
Size
32-bit

ALTDEVCFG0ALT CFGCON0 Fuses

Address
0x00805E98
Reset
0x7100000B
Access
read/write
Size
32-bit

ALTFBCFG0ALT NVR BCFG0

Address
0x00805E9C
Reset
0x80000002
Access
read/write
Size
32-bit

ALTFCPN3RESERVED

Address
0x00805EB0
Reset
0xFFFFFFFF
Access
read/write
Size
32-bit

ALTFCPN2RESERVED

Address
0x00805EB4
Reset
0xFFFFFFFF
Access
read/write
Size
32-bit

ALTFCPN1RESERVED

Address
0x00805EB8
Reset
0xFFFFFFFF
Access
read/write
Size
32-bit

ALTFCPN0ALT NVR CPN Register

Address
0x00805EBC
Reset
0x10000000
Access
read/write
Size
32-bit

FBCFG7RESERVED

Address
0x00805F80
Reset
0xFFFFFFFF
Access
read/write
Size
32-bit

FBCFG6RESERVED

Address
0x00805F84
Reset
0xFFFFFFFF
Access
read/write
Size
32-bit

FUSERIDUSER Page USERID

Address
0x00805F88
Reset
0x0000FFFF
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
USER_ID15:0User unique ID, readable using the SWD USER_ID instruction

DEVCFG4USER Page CFGCON4 Fuses

Address
0x00805F8C
Reset
0x840E4000
Access
read/write
Size
32-bit
17 fields
FieldBitsWhat it does
LPOSCEN30Low Power (Secondary) Oscillator Enable
  • 0 Disable
  • 1 Enabled
UVREGROVR29ULPVREG Retention Mode Override
  • 0 ULPVREG controlled by XDS/DS FSM
  • 1 ULPVREG forced in retention mode
DSEN28Deep Sleep Bit Enable
  • 0 Disable DS Bit in DSCON
  • 1 Enable DS Bit in DSCON
DSWDTEN27Deep Sleep Watchdog Timer Enable
  • 0 Disabled
  • 1 Enabled
DSWDTOSC26Deep Sleep Watchdog Timer Reference Clock Select
  • 0 Select SOSC as DSWDT Reference Clock
  • 1 Select LPRC as DSWDT Reference Clock
DSWDTPS25:21Deep Sleep Watchdog Timer Postscale Select
  • 0 1:32(1ms)
  • 1 1:64(2.1ms)
  • 2 1:128(4.1ms)
  • 3 1:256(8.3ms)
  • 4 1:512(16.5ms)
  • 5 1:1024(33ms)
  • 6 1:2048(66.1ms)
  • 7 1:4096(132.1ms)
  • 8 1:8192(264.3ms)
  • 9 1:16384(528.5ms)
  • 10 1:32768(1.057s)
  • 11 1:65536(2.114s)
  • 12 1:2^17(4.288s)
  • 13 1:2^18(8.456s)
  • 14 1:2^19(16.912s)
  • 15 1:2^20(33.825s)
  • 16 1:2^21(67.7s)
  • 17 1:2^22(135.3s)
  • 18 1:2^23(4.5 minutes)
  • 19 1:2^24(9.0 minutes)
  • 20 1:2^25(18.0 minutes)
  • 21 1:2^26(36.1 minutes)
  • 22 1:2^27(72.2 minutes)
  • 23 1:2^28(2.4 hours)
  • 24 1:2^29(4.8 hours)
  • 25 1:2^30(9.6 hours)
  • 26 1:2^31(19.2 hours)
  • 27 1:2^32(38.5 hours)
  • 28 1:2^33(77.0 hours)
  • 29 1:2^34(6.4 days)
  • 30 1:2^35(12.8 days)
  • 31 1:2^36(25.7 days)
DSZPBOREN20Deep Sleep Zero-Power BOR Enable
  • 0 Disabled
  • 1 Enabled
CPEN_DLY19:17Charge-pump ready digital delay
  • 0 1 LPRC Clock Cycle Delay
  • 1 2 LPRC Clock Cycle Delay
  • 2 3 LPRC Clock Cycle Delay
  • 3 4 LPRC Clock Cycle Delay
  • 4 5 LPRC Clock Cycle Delay
  • 5 6 LPRC Clock Cycle Delay
  • 6 7 LPRC Clock Cycle Delay
  • 7 8 LPRC Clock Cycle Delay
RTCEVTYPE16RTC Event Type
  • 0 RTC_OUT
  • 1 RTC_EVENT
LPCLK_MOD15LPCLK modifier in counter/delay mode
  • 0 Divide-by 1 (Recommended when LPCLK=32kHz)
  • 1 Divide-by 1.024 (Recommended when LPCLK=32.768kHz)
VBKP_DIVSEL14VDDBUKPCORE LPCLK Clock Divider Selection
  • 0 Divide-by 32 (Recommended when LPCLK=32.768kHz))
  • 1 Divide by 31.25 (Recommended when LPCLK=32kHz)
VBKP_32KCSEL13:12VDDBUKPCORE 32kHz clock source selection
  • 0 FRC
  • 1 POSC
  • 2 SOSC
  • 3 LPRC
VBKP_1KCSEL11VDDBUKPCORE LPCLK Clock Selection
  • 0 32kHz low power clock
  • 1 Divide by 32 or 31.25 clock depending on VBKP_DIVSEL
RTCEVENT_EN10Pad Output Enable for MCHP legacy RTC event output
  • 0 Disable RTC Event
  • 1 Enable RTC Event
RTCEVENT_SEL9:8RTC Event Selection
  • 0 1-Second Clock
  • 1 Alarm Pulse
  • 2 32 kHz Clock
SOSCCFG7:0SOSC Configuration
RTCNTM_CSEL31RTC Counter Mode Clock Select
  • 0 Processed 32kHz clock
  • 1 Raw 32kHz clock

DEVCFG2USER Page CFGCON2 Fuses

Address
0x00805F90
Reset
0x5F74FF38
Access
read/write
Size
32-bit
16 fields
FieldBitsWhat it does
DMTCNT30:26Dead Man Timer Count Select
  • 0 2^8 (256)
  • 1 2^9 (512)
  • 2 2^10 (1024)
  • 3 2^11 (2048)
  • 4 2^12 (4096)
  • 5 2^13 (8192)
  • 6 2^14 (16384)
  • 7 2^15 (32768)
  • 8 2^16 (65536)
  • 9 2^17 (131072)
  • 10 2^18 (262144)
  • 11 2^19 (524288)
  • 12 2^20 (1048576)
  • 13 2^21 (2097152)
  • 14 2^22 (4194304)
  • 15 2^23 (8388608)
  • 16 2^24 (16777216)
  • 17 2^25 (33554432)
  • 18 2^26 (67108864)
  • 19 2^27 (134217728)
  • 20 2^28 (268435456)
  • 21 2^29 (536870912)
  • 22 2^30 (1073741824)
  • 23 2^31 (2147483648)
WDTWINSZ25:24Watchdog Timer Window Size
  • 0 Window size is 75%
  • 1 Window size is 50%
  • 2 Window size is 37.5%
  • 3 Window size is 25%
WDTEN23Watchdog Timer Enable
  • 0
  • 1
WINDIS22Windowed Watchdog Timer Disable
  • 0
  • 1
WDTSPGM21Watchdog Timer Stop during Flash Programming
  • 0
  • 1
WDTPSR20:16Watchdog Timer Post-scale Select Run
  • 0 1:1
  • 1 1:2
  • 2 1:4
  • 3 1:8
  • 4 1:16
  • 5 1:32
  • 6 1:64
  • 7 1:128
  • 8 1:256
  • 9 1:512
  • 10 1:1024
  • 11 1:2048
  • 12 1:4096
  • 13 1:8192
  • 14 1:16384
  • 15 1:32768
  • 16 1:65536
  • 17 1:131072
  • 18 1:262144
  • 19 1:524288
  • 20 1:1048576
FSCMEN15Fail-Safe Clock Monitor Enable
  • 0
  • 1
CKSWEN14Software Clock Switching Enable
  • 0
  • 1
WAKE2SPD132-Speed startup enabled in Sleep mode
  • 0
  • 1
SOSCSEL12SOSC Selection Configuration
  • 0
  • 1
WDTRMCS11:10WDT RUN Mode Clock Select
  • 0 SYSCLK
  • 3 LPRC
POSCMOD9:8Primary Oscillator Configuration
  • 0
  • 3
PMUTEST_VDD_EN7PMU Test Output or VDD/2 Enable via ADC IE12
  • 0 VDD_div_2 Monitor
  • 1 PMU Test Output Monitor
DMTINTV5:3Dead Man Timer Count Window Interval
  • 0 Window/Interval value is zero
  • 1 Window/Interval value is 1/2 counter value
  • 2 Window/Interval value is 3/4 counter value
  • 3 Window/Interval value is 7/8 counter value
  • 4 Window/Interval value is 15/16 counter value
  • 5 Window/Interval value is 31/32 counter value
  • 6 Window/Interval value is 63/64 counter value
  • 7 Window/Interval value is 127/128 counter value
ACMP_CYCLE2:0AC Comparator Result Wait Cycles
  • 0 32us
  • 1 64us
  • 2 96us
  • 3 128us
  • 4 160us
  • 5 196us
  • 6 224us
  • 7 256us
DMTEN31Dead Man Timer Enable
  • 0
  • 1

DEVCFG1USER Page CFGCON1 Fuses

Address
0x00805F94
Reset
0x1410443B
Access
read/write
Size
32-bit
18 fields
FieldBitsWhat it does
CLKZBREF30External Reference Clock ZB Enable
  • 0
  • 1
QSPIDDRM29QSPI DDR Mode Clock Enable
  • 0
  • 1
WDTPSS28:24Watchdog Timer Post-scale Select Sleep
  • 0 1:1
  • 1 1:2
  • 2 1:4
  • 3 1:8
  • 4 1:16
  • 5 1:32
  • 6 1:64
  • 7 1:128
  • 8 1:256
  • 9 1:512
  • 10 1:1024
  • 11 1:2048
  • 12 1:4096
  • 13 1:8192
  • 14 1:16384
  • 15 1:32768
  • 16 1:65536
  • 17 1:131072
  • 18 1:262144
  • 19 1:524288
  • 20 1:1048576
I2CDSEL122I2C Delay Select for SERCOM1
  • 0
  • 1
I2CDSEL021I2C Delay Select for SERCOM0
  • 0
  • 1
CCL_OE20CCL Pads (via PPS) Output Enable
  • 0
  • 1
SCOM1_HSEN18SERCOM1 Direct (High Speed) Pin Enable
  • 0
  • 1
SCOM0_HSEN17SERCOM0 Direct (High Speed) Pin Enable
  • 0
  • 1
QSPI_HSEN16QSPI Direct (High Speed) Pin Enable
  • 0
  • 1
QSCHE_EN15QSPI Address Space Cache Attribute
  • 0
  • 1
SMCLR14Selects CRU handling of MCLR Control
  • 0
  • 1
SLRCTRL112I2C Slew Rate Control for SERCOM1
  • 0
  • 1
SLRCTRL011I2C Slew Rate Control for SERCOM0
  • 0
  • 1
CMP1_OE9Analog Comparator-1 Output Enable
  • 0
  • 1
CMP0_OE8Analog Comparator-0 Output Enable
  • 0
  • 1
ZBTWKSYS7ZBT Subsystem External Wake-up source
  • 0
  • 1
ECC_SEL_MEM6ECC row selection bit
  • 0
  • 1
TRCEN5Trace Enable
  • 0
  • 1

DEVCFG0USER Page CFGCON0 Fuses

Address
0x00805F98
Reset
0x7100000B
Access
read/write
Size
32-bit
17 fields
FieldBitsWhat it does
FRECCDIS30Flex RAM ECC Control
  • 0
  • 1
FECCCON29:28Flash ECC Control
  • 0
  • 1
  • 3
INT0P26INT0P Polarity
  • 0
  • 1
INT0E25INT0 Enable
  • 0
  • 1
PCM24PCHE I/D Cacheable Mode
  • 0
  • 1
SLRTEN122SLRT Enable for SERCOM1
  • 0
  • 1
SLRTEN021SLRT Enable for SERCOM0
  • 0
  • 1
HPLUGDIS20Hot Plugging Disable
  • 0
  • 1
SMBUSEN118SMBus Enable for SERCOM1
  • 0
  • 1
SMBUSEN017SMBus Enable for SERCOM0
  • 0
  • 1
RTCOUT_ALTEN9RTCOUT Alternate Enable
  • 0
  • 1
RTCIN0_ALTEN8RTCIN0 Alternate Enable
  • 0
  • 1
CPENFILT7ADC CP Filter Enable
  • 0
  • 1
ACCMP1_ALTEN6AC CMP1 Alternate Enable
  • 0
  • 1
ADCPOVR4ADC Charge Pump Override
  • 0
  • 1
TROEN2Trace Output Enable
  • 0
  • 1
SWOEN1SWO enable on 2-wire debug interface
  • 0
  • 1

FBCFG0NVR BCFG User Configuration Area

Address
0x00805F9C
Reset
0x00000002
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
PCSCMODE1PCache Single cache Mode
  • 0 PCHE ICache and DCache. CPU opcodes go to PCEHE ICache port and data goes to PCHE
  • 1 PCHE ICache Only.CPU Instructions (code, data) go to PCHE ONLY.
BINFOVALID31BCFG info valid
  • 0 BCFG0 to BCFG7 is valid.
  • 1 BCFG0 to BCFG7 is not valid.

FCPN3RESERVED

Address
0x00805FB0
Reset
0xFFFFFFFF
Access
read/write
Size
32-bit

FCPN2RESERVED

Address
0x00805FB4
Reset
0xFFFFFFFF
Access
read/write
Size
32-bit

FCPN1RESERVED

Address
0x00805FB8
Reset
0xFFFFFFFF
Access
read/write
Size
32-bit

FCPN0NVR CPN Register

Address
0x00805FBC
Reset
0x10000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CP28Boot Code Protect
  • 0 Protection Enabled
  • 1 Protection Disabled